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femtoampere input bias current electrometer amplifier data sheet ada4530-1 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015C2016 analog devices, inc. all rights reserved. technical support www.analog.com features low input bias current 20 fa maximum at t a = 25c (guaranteed at production test) 20 fa maximum at ?40c < t a < +85c 250 fa maximum at ?40c < t a < +125c (guaranteed at production test) low offset voltage: 50 v maximum over specified cmrr range offset drift: 0.13 v/c typical, 0.5 v/c maximum integrated guard buffer with 100 v maximum offset low voltage noise density: 14 nv/hz at 10 khz wide bandwidth: 2 mhz unity-gain crossover supply voltage: 4.5 v to 16 v (2.25 v to 8 v) operating temperature: ?40c to +125c applications laboratory and analytical instrumentation: spectrophotometers, chromatographs, mass spectrometers, and potentio static and amperostatic coulometry instrumentation: picoammeters and coulombmeters transimpedance amplifier (tia) for photodiodes, ion chambers, and working electrode measurements high impedance buffering for chemical sensors and capacitive sensors pin connection diagram +in 1 grd 2 ic 3 v? 4 ?in 8 grd 7 out 6 v+ 5 a da4530-1 13405-001 notes 1. ic = internal connection. this pin must be connected to v? or left unconnected. figure 1. general description the ada4530-1 is a femtoampere (10 ?15 a) level input bias current operational amplifier suitable for use as an electrometer that also includes an integrated guard buffer. it has an operating voltage range of 4.5 v to 16 v enabling it to operate in conven- tional 5 v and 10 v single supply systems as well as 2.5 v and 5 v dual supply systems. it provides ultralow input bias currents that are production tested at temperature to ensure the device meets its perfor- mance goals in user systems. the integrated guard buffer is provided to isolate the input pins from leakage in the printed circuit board (pcb), minimize board component count, and enable ease of system design. the ada4530-1 is available in an industry-standard surface-mount 8-lead soic package with a unique pinout optimized to prevent signals from coupling between the sensitive input pins, the power supplies, and the output pin while enabling easy routing of the guard ring traces. the ada4530-1 also offers low offset voltage, low offset drift, and low voltage and current noise needed for the types of applications that require such low leakages. to maximize the dynamic range of the system, the ada4530-1 has a rail-to-rail output stage that can typically drive to within 30 mv of the supply rails under a 10 k load. the ada4530-1 operates over the ?40c to +125c industrial temperature range and is available in an 8-lead soic package. 13405-202 1000 0.001 0.01 0.1 1 10 100 010 30 20 40 50 60 70 80 90 100 110 120 130 i b (fa) temperature (c) v sy = 10v v cm = v sy /2 rh < 10% ?40c to +85c limit ?40c to +125c limit i b + i b ? figure 2. input bias current (i b ) vs. temperature, v sy = 10 v
ada4530-1* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ada4530-1 evaluation board documentation application notes ? an-1373: ada4530-1 femtoampere level input bias current measurement user guides ? ug-865: ada4530-1 8-lead soic package evaluation board tools and simulations ? ada4530 spice macro-model reference materials press ? electrometer-grade amplifier improves accuracy while reducing size of chemical analysis instruments design resources ? ada4530-1 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ada4530-1 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ada4530-1 data sheet rev. a | page 2 of 50 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin connection diagram ................................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v nominal electrical characteristics ..................................... 3 ? 10 v nominal electrical characteristics ................................... 5 ? 15 v nominal electrical characteristics ................................... 7 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 11 ? main amplifier, dc performance ............................................ 11 ? main amplifier, ac performance ............................................ 20 ? guard amplifier ......................................................................... 26 ? theory of operation ...................................................................... 28 ? esd structure .............................................................................. 28 ? input stage ................................................................................... 28 ? gain stage .................................................................................... 29 ? output stage ................................................................................ 29 ? guard buffer ............................................................................... 29 ? applications information .............................................................. 30 ? input protection .......................................................................... 30 ? single-supply and rail-to-rail output ................................... 30 ? capacitive load stability ........................................................... 30 ? emi rejection ratio ................................................................... 31 ? high impedance measurements ................................................... 32 ? input bias current ...................................................................... 32 ? input resistance .......................................................................... 33 ? input offset voltage ................................................................... 33 ? insulation resistance ................................................................. 33 ? guarding ...................................................................................... 34 ? dielectric relaxation .................................................................. 34 ? humidity effects ......................................................................... 36 ? contamination ............................................................................ 37 ? cleaning and handling ............................................................. 38 ? solder paste selection ................................................................ 38 ? current noise considerations ...................................................... 39 ? layout guidelines ........................................................................... 42 ? physical implementation of guarding techniques................ 42 ? guard ring .................................................................................. 42 ? guard plane ................................................................................. 42 ? via fence ..................................................................................... 43 ? cables and connectors .............................................................. 43 ? electrostatic interferance .......................................................... 43 ? photodiode interface ...................................................................... 44 ? dc error analysis ...................................................................... 44 ? ac error analysis ...................................................................... 44 ? noise analysis ............................................................................. 45 ? design recommendations ........................................................ 46 ? design example .......................................................................... 46 ? power supply recommendations ................................................. 49 ? power supply considerations ................................................... 49 ? outline dimensions ....................................................................... 50 ? ordering guide .......................................................................... 50 ? revision history 3/16rev. 0 to rev. a changed dnc pin to ic pin ........................................ throughout changes to figure 1 .......................................................................... 1 changes to figure 3 and table 6 ................................................... 10 changes to figure 29 ...................................................................... 15 changes to theory of operation section .................................... 28 changes to humidity effects section and figure 112 ............... 36 added power supply recommendations section, power supply considerations section, table 16, and figure 133 to figure 135 ........................................................................................ 49 10/15revision 0: initial version
data sheet ada4530-1 rev. a | page 3 of 50 specifications 5 v nominal electrical characteristics v sy = 4.5 v, v cm = v sy /2, t a = 25c, unless otherwise specified. typical specifications are equal to the average of the distribution from characterization, unless otherwise noted. minimum and maximum specifications are tested in production, unless otherwise noted. table 1. parameter 1 symbol test conditions/comments min typ max unit input characteristics input bias current 2, 3 i b rh < 50% <1 20 fa ?40c < t a < +85c, rh < 50% 20 fa ?40c < t a < +125c, rh < 50% 250 fa input offset current 3 i os rh < 50% <1 20 fa ?40c < t a < +125c, rh < 50% 150 fa offset voltage 2, 4 v os +8 40 v v cm = 1.5 v to 3 v +9 50 v v cm = 1.5 v to 3 v, 0c < t a < 125c 70 v v cm = 1.5 v to 3 v, ?40c < t a < 0c 150 v v cm = 0 v to 3 v 300 v offset voltage drift 2, 4 v os /t 0c < t a < 125c +0.13 0.5 v/c ?40c < t a < 0c ?0.7 2.8 v/c input voltage range ivr 0 3 v common-mode rejection ratio cmrr v cm = 1.5 v to 3 v 92 114 db ?40c < t a < +125c 90 db v cm = 0 v to 3 v 73 db large signal voltage gain a vo r l = 2 k to v cm , v out = 0.2 v to 4.3 v 120 143 db ?40c < t a < +125c 120 db input resistance r in ?40c < t a < +125c >100 t input capacitance c in 8 pf output characteristics output voltage high v oh r l = 10 k to v cm 4.47 4.49 v ?40c < t a < +125c 4.46 v r l = 2 k to v cm 4.4 4.45 v ?40c < t a < +125c 4.38 v output voltage low v ol r l = 10 k to v cm 10 30 mv ?40c < t a < +125c 40 mv r l = 2 k to v cm 30 100 mv ?40c < t a < +125c 120 mv short-circuit current i sc source 15 ma sink ?30 ma closed-loop output impedance z out f = 1 mhz, a v = 1 20 power supply power supply rejection ratio psrr v sy = 4.5 v to 16 v 130 150 db ?40c < t a < +125c 130 db supply current i sy i out = 0 ma 0.9 1.3 ma ?40c < t a < +125c 1.5 ma dynamic performance slew rate sr r l = 10 k, c l = 10 pf, a v = 1 1.4 v/s gain bandwidth product gbp v in = 10 mv rms, r l = 10 k, c l = 10 pf, a v = 100 2 mhz unity-gain crossover ugc v in = 10 mv rms, r l = 10 k, c l = 10 pf, a vo = 1 2 mhz ?3 db closed-loop bandwidth f ?3db v in =10 mv rms, r l = 10 k, c l = 10 pf, a v = 1 6 mhz
ada4530-1 data sheet rev. a | page 4 of 50 parameter 1 symbol test conditions/comments min typ max unit phase margin m v in = 10 mv rms, r l = 10 k, c l = 10 pf, a vo = 1 62 degrees settling time to 0.1% t s v in = 0.5 v step, r l = 10 k, c l = 10 pf, a v = ?1 5 s emi rejection ratio of +in emirr v in = 100 mv peak, f = 400 mhz 50 db v in = 100 mv peak, f = 900 mhz 60 db v in = 100 mv peak, f = 1800 mhz 80 db v in = 100 mv peak, f = 2400 mhz 90 db noise performance peak-to-peak voltage noise e n p-p f = 0.1 hz to 10 hz 4 v p-p voltage noise density e n f = 10 hz 80 nv/hz f = 1 khz 16 nv/hz f = 10 khz 14 nv/hz current noise density i n f = 0.1 hz 0.07 fa/hz total harmonic distortion + noise thd + n a v = 1, f = 1 khz, v in = 0.5 v rms bandwidth = 90 khz 0.003 % bandwidth = 500 khz 0.0045 % guard buffer guard offset voltage 2, 4, 5 v gos v cm = 1.5 v to 3 v 15 100 v v cm = 1.5 v to 3 v, 0c < t a < 125c 120 v v cm = 1.5 v to 3 v, ?40c < t a < 0c 250 v v cm = 0.1 v to 3 v 150 v guard offset voltage drift 2, 4 v gos /t 0c < t a < +125c 0.18 1 v/c ?40c < t a < 0c 1.4 7 v/c output impedance z gout 1 k output voltage range v gos < 150 v 0.1 3 v ?3 db bandwidth f ?3dbguard v in = 10 mv rms, c l = 10 pf 5.5 mhz 1 these specifications represent the perfor mance for 5 v 10% power supplies. all spec ifications are measured at the worst case 4.5 v supply voltage. 2 the maximum specifications at ?40c < t a < +85c and ?40c < t a < 0c are guaranteed from characterization. 3 rh is relative humidity (see the humidit y effects section for more information). 4 the typical specifications are equal to the average plus the standard deviation of the distribution from characterization. 5 the guard offset voltage is the voltage difference between the guard output and the noninverting input.
data sheet ada4530-1 rev. a | page 5 of 50 10 v nominal electrical characteristics v sy = 10 v, v cm = v sy /2, t a = 25c, unless otherwise noted. typical specifications are equal to the average of the distribution from characterization, unless otherwise noted. minimum and maximum specifications are tested in production, unless otherwise noted. table 2. parameter 1 symbol test conditions/comments min typ max unit input characteristics input bias current 2, 3 i b rh < 50% <1 20 fa ?40c < t a < +85c, rh < 50% 20 fa ?40c < t a < +125c, rh < 50% 250 fa input offset current 3 i os rh < 50% <1 20 fa ?40c < t a < +125c, rh < 50% 150 fa offset voltage 2, 4 v os +8 40 v v cm = 1.5 v to 8.5 v +9 50 v v cm = 1.5 v to 8.5 v, 0c < t a < 125c 70 v v cm = 1.5 v to 8.5 v, ?40c < t a < 0c 150 v v cm = 0 v to 8.5 v 300 v offset voltage drift 2, 4 v os /t 0c < t a < 125c +0.13 0.5 v/c ?40c < t a < 0c ?0.7 2.8 v/c input voltage range ivr 0 8.5 v common-mode rejection ratio cmrr v cm = 1.5 v to 8.5 v 105 114 db ?40c < t a < +125c 100 db v cm = 0 v to 8.5 v 87 db large signal voltage gain a vo r l = 2 k to v cm , v out = 0.5 v to 9.5 v 125 150 db ?40c < t a < +125c 125 db input resistance r in ?40c < t a < +125c >100 t input capacitance c in 8 pf output characteristics output voltage high v oh r l = 10 k to v cm 9.96 9.97 v ?40c < t a < +125c 9.94 v r l = 2 k to v cm 9.93 9.87 v ?40c < t a < +125c 9.75 v output voltage low v ol r l = 10 k to v cm 15 40 mv ?40c < t a < +125c 60 mv r l = 2 k to v cm 70 170 mv ?40c < t a < +125c 250 mv short-circuit current i sc source 15 ma sink ?30 ma closed-loop output impedance z out f = 1 mhz, a v = 1 20 power supply power supply rejection ratio psrr v sy = 4.5 v to 16 v 130 150 db ?40c < t a < +125c 130 db supply current i sy i out = 0 ma 0.9 1.3 ma ?40c < t a < +125c 1.5 ma dynamic performance slew rate sr r l = 10 k, c l = 10 pf, a v = 1 1.4 v/s gain bandwidth product gbp v in = 10 mv rms, r l = 10 k, c l = 10 pf, a v = 100 2 mhz unity-gain crossover ugc v in = 10 mv rms, r l = 10 k, c l = 10 pf, a vo = 1 2 mhz ?3 db closed-loop bandwidth f ?3db v in = 10 mv rms, r l = 10 k, c l = 10 pf, a v = 1 6 mhz phase margin m v in = 10 mv rms, r l = 10 k, c l = 10 pf, a vo = 1 62 degrees
ada4530-1 data sheet rev. a | page 6 of 50 parameter 1 symbol test conditions/comments min typ max unit settling time to 0.1% t s v in = 1 v step, r l = 10 k, c l = 10 pf, a v = ?1 6 s emi rejection ratio of +in emirr v in = 100 mv peak, f = 400 mhz 50 db v in = 100 mv peak, f = 900 mhz 60 db v in = 100 mv peak, f = 1800 mhz 80 db v in = 100 mv peak, f = 2400 mhz 90 db noise performance peak-to-peak voltage noise e n p-p f = 0.1 hz to 10 hz 4 v p-p voltage noise density e n f = 10 hz 80 nv/hz f = 1 khz 16 nv/hz f = 10 khz 14 nv/hz current noise density i n f = 0.1 hz 0.07 fa/hz total harmonic distortion + noise thd + n a v = 1, f = 1 khz, v in = 2 v rms bandwidth = 90 khz 0.0015 % bandwidth = 500 khz 0.0025 % guard buffer guard offset voltage 2, 4, 5 v gos v cm = 1.5 v to 8.5 v 15 100 v v cm = 1.5 v to 8.5 v, 0c < t a < 125c 120 v v cm = 1.5 v to 8.5 v, ?40c < t a < 0c 250 v v cm = 0.1 v to 8.5 v 150 v guard offset voltage drift 2, 4 v gos /t 0c < t a < 125c 0.18 1 v/c ?40c < t a < 0c 1.4 7 v/c output impedance z gout 1 k output voltage range v gos < 150 v 0.1 8.5 v ?3 db bandwidth f ?3dbguard v in = 10 mv rms, c l = 10 pf 5.5 mhz 1 these specifications represent the perfor mance for 10 v 10% power supplies. all spec ifications are measured at the 10 v supp ly voltage. 2 the maximum specifications at ?40c < t a < +85c and ?40c < t a < 0c are guaranteed from characterization. 3 rh is relative humidity (see the humidit y effects section for more information). 4 these typical specifications are equal to the average plus the standard deviation of the distribution from characterization. 5 the guard offset voltage is the voltage difference between the guard output and the noninverting input.
data sheet ada4530-1 rev. a | page 7 of 50 15 v nominal electrical characteristics v sy = 16 v, v cm = v sy /2, t a = 25c, unless otherwise noted. typical specifications are equal to the average of the distribution from characterization, unless otherwise noted. minimum and maximum specifications are tested in production, unless otherwise noted. table 3. parameter 1 symbol test conditions/comments min typ max unit input characteristics input bias current 2, 3 i b rh < 50% <1 20 fa ?40c < t a < +85c, rh < 50% 20 fa ?40c < t a < +125c, rh < 50% 250 fa input offset current i os rh < 50% <1 20 fa ?40c < t a < +125c, rh < 50% 150 fa offset voltage 2, 4 v os +8 40 v v cm = 1.5 v to 14.5 v +9 50 v v cm = 1.5 v to 14.5 v, 0c < t a < 125c 70 v v cm = 1.5 v to 14.5 v, ?40c < t a < 0c 150 v v cm = 0 v to 14.5 v 300 v offset voltage drift 2, 4 v os /t 0c < t a < 125c +0.13 0.5 v/c ?40c < t a < 0c ?0.7 2.8 v/c input voltage range ivr 0 14.5 v common-mode rejection ratio cmrr v cm = 1.5 v to 14.5 v 110 114 db ?40c < t a < +125c 105 db v cm = 0 v to 14.5 v 93 db large signal voltage gain a vo r l = 2 k to v cm , v out = 0.5 v to 15.5 v 130 155 db ?40c < t a < +125c 125 db input resistance r in ?40c < t a < +125c >100 t input capacitance c in 8 pf output characteristics output voltage high v oh r l = 10 k to v cm 15.93 15.95 v ?40c < t a < +125c 15.9 v r l = 2 k to v cm 15.72 15.78 v ?40c < t a < +125c 15.58 v output voltage low v ol r l = 10 k to v cm 25 70 mv ?40c < t a < +125c 100 mv r l = 2 k to v cm 115 280 mv ?40c < t a < +125c 420 mv short-circuit current i sc source 15 ma sink ?30 ma closed-loop output impedance z out f = 1 mhz, a v = 1 20 power supply power supply rejection ratio psrr v sy = 4.5 v to 16 v 130 150 db ?40c < t a < +125c 130 db supply current i sy i out = 0 ma 0.9 1.3 ma ?40c < t a < +125c 1.5 ma dynamic performance slew rate sr r l = 10 k, c l = 10 pf, a v = 1 1.4 v/s gain bandwidth product gbp v in = 10 mv rms, r l = 10 k, c l = 10 pf, a v = 100 2 mhz unity-gain crossover ugc v in = 10 mv rms, r l = 10 k, c l = 10 pf, a vo = 1 2 mhz ?3 db closed-loop bandwidth f ?3 db v in = 10 mv rms, r l = 10 k, c l = 10 pf, a v = 1 6 mhz phase margin m v in =10 mv rms, r l = 10 k, c l = 10 pf, a vo = 1 62 degrees
ada4530-1 data sheet rev. a | page 8 of 50 parameter 1 symbol test conditions/comments min typ max unit settling time to 0.1% t s v in = 1 v step, r l = 10 k, c l = 10 pf, a v = ?1 6 s emi rejection ratio of +in emirr v in = 100 mv peak, f = 400 mhz 50 db v in = 100 mv peak, f = 900 mhz 60 db v in = 100 mv peak, f = 1800 mhz 80 db v in = 100 mv peak, f = 2400 mhz 90 db noise performance peak-to-peak voltage noise e n p-p f = 0.1 hz to 10 hz 4 v p-p voltage noise density e n f = 10 hz 80 nv/hz e n f = 1 khz 16 nv/hz e n f = 10 khz 14 nv/hz current noise density i n f = 0.1 hz 0.07 fa/hz total harmonic distortion + noise thd + n a v = 1, f = 1 khz, v in = 4.5 v rms bandwidth = 90 khz 0.0012 % bandwidth = 500 khz 0.003 % guard buffer guard offset voltage 4, 5 v gos v cm = 1.5 v to 14.5 v 15 100 v v cm = 1.5 v to 14.5 v, 0c < t a < 125c 120 v v cm = 1.5 v to 14.5 v, ?40c < t a < 0c 250 v v cm = 0.1 v to 14.5 v 150 v guard offset voltage drift 2, 4 v gos /t 0c < t a < +125c 0.18 1 v/c ?40c < t a < 0c 1.4 7 v/c output impedance z gout 1 k output voltage range v gos < 150 v 0.1 14.5 v ?3 db bandwidth f ?3 db guard v in = 10 mv rms, c l = 10 pf 5.5 mhz 1 these specifications represent the perfor mance for 15 v 1 v power supplies. all spec ifications are measured at the worst cas e 16 v supply voltage. 2 the maximum specifications at ?40c < t a < +85c and ?40c < t a < 0c are guaranteed from characterization. 3 rh is relative humidity (see the humidit y effects section for more information). 4 these typical specifications are equal to the average plus the standard deviation of the distribution from characterization. 5 the guard offset voltage is the voltage difference between the guard output and the noninverting input.
data sheet ada4530-1 rev. a | page 9 of 50 absolute maximum ratings table 4. parameter rating supply voltage 17 v input voltage (v?) ? 0.3 v to (v+) + 0.3 v input current 1 10 ma differential input voltage 0.7 v output short-circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c esd human body model 2 4 kv field induced charged device model (ficdm) 3 1.25 kv 1 the input pins have clamp diodes to the power supply pi ns. limit the input current to 10 ma or less whenever in put signals exceed the power supply rail by 0.3 v. 2 applicable standard esda/jedec js-001-2012. 3 applicable standard jesd22-c101-e (esd ficdm standard of jedec). stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages using a standard 4-layer jedec board. table 5. thermal resistance package type ja jc unit 8-lead soic 122 41 c/w esd caution
ada4530-1 data sheet rev. a | page 10 of 50 pin configuration and function descriptions +in 1 grd 2 ic 3 v? 4 ?in 8 grd 7 out 6 v+ 5 a da4530-1 13405-003 notes 1. ic = internal connection. this pin must be connected to v? or left unconnected. figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 +in noninverting input. 2 grd guard. 3 ic internal connection. this pin must be connected to v? or left unconnected. 4 v? negative supply voltage. 5 v+ positive supply voltage. 6 out output. 7 grd guard. 8 ?in inverting input.
data sheet ada4530-1 rev. a | page 11 of 50 typical performance characteristics main amplifier, dc performance t a = 25c, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 24 28 32 36 40 number of amplifiers v os (v) v sy = 4.5v v cm = v sy /2 590 channels x = 2.31v = 5.48v 13405-004 figure 4. input offset voltage distribution, v sy = 4.5 v 100 90 80 70 60 50 40 30 20 10 0 ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 24 28 32 36 40 number of amplifiers v os (v) v sy = 10v v cm = v sy /2 590 channels x = 2.27v = 5.45v 13405-005 figure 5. input offset voltage distribution, v sy = 10 v 100 90 80 70 60 50 40 30 20 10 0 ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 24 28 32 36 40 number of amplifiers v os (v) v sy = 16v v cm = v sy /2 590 channels x = 2.15v = 5.47v 13405-006 figure 6. input offset voltage distribution, v sy = 16 v 80 60 40 20 0 ?20 ?40 ?60 ?50 ?25 0 25 50 75 100 125 v os (v) temperature (c) v sy = 4.5v v cm = v sy /2 574 channels 13405-007 figure 7. input offset voltage (v os ) vs. temperature, v sy = 4.5 v 80 60 40 20 0 ?20 ?40 ?60 ?50 ?25 0 25 50 75 100 125 v os (v) temperature (c) v sy = 10v v cm = v sy /2 574 channels 13405-008 figure 8. input offset voltage (v os ) vs. temperature, v sy = 10 v 80 60 40 20 0 ?20 ?40 ?60 ?50 ?25 0 25 50 75 100 125 v os (v) temperature (c) v sy = 16v v cm = v sy /2 574 channels 13405-009 figure 9. input offset voltage (v os ) vs. temperature, v sy = 16 v
ada4530-1 data sheet rev. a | page 12 of 50 tcv os (v/c) 120 100 80 60 40 20 0 number of amplifiers ?2.8 ?2.4 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 v sy = 4.5v v cm = v sy /2 574 channels ?40c t a 0c x = ?0.29v/c = 0.42v/c 13405-013 figure 10. input offset voltage drift distribution, ?40c t a 0c, v sy = 4.5 v tcv os (v/c) 120 100 80 60 40 20 0 number of amplifiers ?2.8 ?2.4 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 v sy = 10v v cm = v sy /2 574 channels ?40c t a 0c x = ?0.29v/c = 0.42v/c 13405-014 figure 11. input offset voltage drift distribution, ?40c t a 0c, v sy = 10 v tcv os (v/c) 120 100 80 60 40 20 0 number of amplifiers ?2.8 ?2.4 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 v sy = 16v v cm = v sy /2 574 channels ?40c t a 0c x = ?0.29v/c = 0.41v/c 13405-015 figure 12. input offset voltage drift distribution, ?40c t a 0c, v sy = 16 v 120 100 80 60 40 20 0 ?0.5 ?0.4 ?0.3 ?0.2 ?1.0 0 0.1 0.2 0.3 0.4 0.5 number of amplifiers tcv os (v/c) v sy = 4.5v v cm = v sy /2 574 channels 0c t a 125c x = ?0.025v/c = 0.107v/c 13405-010 figure 13. input offset voltage drift distribution, 0c t a 125c, v sy = 4.5 v 120 100 80 60 40 20 0 ?0.5 ?0.4 ?0.3 ?0.2 ?1.0 0 0.1 0.2 0.3 0.4 0.5 number of amplifiers tcv os (v/c) v sy = 10v v cm = v sy /2 574 channels 0c t a 125c x = ?0.025v/c = 0.107v/c 13405-011 figure 14. input offset voltage drift distribution, 0c t a 125c, v sy = 10 v 120 100 80 60 40 20 0 ?0.5 ?0.4 ?0.3 ?0.2 ?1.0 0 0.1 0.2 0.3 0.4 0.5 number of amplifiers tcv os (v/c) v sy = 16v v cm = v sy /2 574 channels 0c t a 125c x = ?0.024v/c = 0.107v/c 13405-012 figure 15. input offset voltage drift distribution, 0c t a 125c, v sy = 16 v
data sheet ada4530-1 rev. a | page 13 of 50 60 40 20 0 ?20 ?40 ?60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v os (v) v cm (v) v sy = 4.5v 590 channels t a = 25c preferred common-mode range 13405-016 figure 16. input offset voltage (v os ) vs. common-mode voltage (v cm ), v sy = 4.5 v 60 40 20 0 ?20 ?40 ?60 012345678910 v os (v) v cm (v) v sy = 10v 590 channels t a = 25c preferred common-mode range 13405-017 figure 17. input offset voltage (v os ) vs. common-mode voltage (v cm ), v sy = 10 v 60 40 20 0 ?20 ?40 ?60 01234567891011121314 16 15 v os (v) v cm (v) v sy = 16v 590 channels t a = 25c preferred common-mode range 13405-018 figure 18. input offset voltage (v os ) vs. common-mode voltage (v cm ), v sy = 16 v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 04500 4000 3500 3000 2500 2000 1500 1000 500 input offset voltage (v) time (hours) v sy = 10v 27 channels t a = 25c 13405-219 figure 19. v os long-term drift 2.5 0 0.5 1.0 1.5 2.0 05 4 3 2 1 input offset voltage (v) time after power-on (minutes) v sy = 10v t a = 25c 13405-220 figure 20. v os warm-up time 0 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 01 0 987654321 small signal cmrr (db) v cm (v) v sy = 10v ? v cm = 400mv preferred common-mode range 13405-221 figure 21. small signal cmrr vs. common-mode voltage
ada4530-1 data sheet rev. a | page 14 of 50 20 ?20 ?15 ?10 ?5 0 5 10 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 i b? (fa) v cm (v) v sy = 4.5v 27 channels t a = 85c preferred common-mode range 13405-022 figure 22. inverting input bias current (i b? ) vs. common-mode voltage (v cm ), v sy = 4.5 v, t a = 85c 20 ?20 ?15 ?10 ?5 0 5 10 15 012345678 10 9 i b? (fa) v cm (v) v sy = 10v 27 channels t a = 85c preferred common-mode range 13405-023 figure 23. inverting input bias current (i b? ) vs. common-mode voltage (v cm ), v sy = 10 v, t a = 85c 20 ?20 ?15 ?10 ?5 0 5 10 15 0246810121416 i b? (fa) v cm (v) v sy = 16v 27 channels t a = 85c preferred common-mode range 13405-024 figure 24. inverting input bias current (i b? ) vs. common-mode voltage (v cm ), v sy = 16 v, t a = 85c 20 ?20 ?15 ?10 ?5 0 5 10 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 i b+ (fa) v cm (v) v sy = 4.5v 27 channels t a = 85c preferred common-mode range 13405-025 figure 25. noninverting input bias current (i b+ ) vs. common-mode voltage (v cm ), v sy = 4.5 v, t a = 85c 20 ?20 ?15 ?10 ?5 0 5 10 15 012345678 10 9 i b+ (fa) v cm (v) v sy = 10v 27 channels t a = 85c preferred common-mode range 13405-026 figure 26. noninverting input bias current (i b+ ) vs. common-mode voltage (v cm ), v sy = 10 v, t a = 85c 20 ?20 ?15 ?10 ?5 0 5 10 15 0246810121416 i b+ (fa) v cm (v) v sy = 16v 27 channels t a = 85c preferred common-mode range 13405-027 figure 27. noninverting input bias current (i b+ ) vs. common-mode voltage (v cm ), v sy = 16 v, t a = 85c
data sheet ada4530-1 rev. a | page 15 of 50 300 ?300 ?200 ?100 0 100 200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 i b? (fa) v cm (v) v sy = 4.5v 27 channels t a = 125c preferred common-mode range 13405-028 figure 28. inverting input bias current (i b? ) vs. common-mode voltage (v cm ), v sy = 4.5 v, t a = 125c 300 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 012345678 10 9 i b? (fa) v cm (v) v sy = 10v 27 channels t a = 125c preferred common-mode range 13405-029 figure 29. inverting input bias current (i b? ) vs. common-mode voltage (v cm ), v sy = 10 v, t a = 125c 300 ?300 ?200 ?100 0 100 200 0246810121416 i b? (fa) v cm (v) v sy = 16v 27 channels t a = 125c preferred common-mode range 13405-030 figure 30. inverting input bias current (i b? ) vs. common-mode voltage (v cm ), v sy = 16 v, t a = 125c 300 ?300 ?200 ?100 0 100 200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 i b+ (fa) v cm (v) v sy = 4.5v 27 channels t a = 125c preferred common-mode range 13405-031 figure 31. noninverting input bias current (i b+ ) vs. common-mode voltage (v cm ), v sy = 4.5 v, t a = 125c 300 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 012345678 10 9 i b+ (fa) v cm (v) v sy = 10v 27 channels t a = 125c preferred common-mode range 13405-032 figure 32. noninverting input bias current (i b+ ) vs. common-mode voltage (v cm ), v sy = 10 v, t a = 125c 300 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 0246810121416 i b+ (fa) v cm (v) v sy = 16v 27 channels t a = 125c preferred common-mode range 13405-033 figure 33. noninverting input bias current (i b+ ) vs. common-mode voltage (v cm ), v sy = 16 v, t a = 125c
ada4530-1 data sheet rev. a | page 16 of 50 1000 0.001 0.01 0.1 1 10 100 010 30 20 40 50 60 70 80 90 100 110 120 130 i b (fa) temperature (c) v sy = 4.5v v cm = v sy /2 rh < 10% ?40c to +85c limit ?40c to +125c limit i b + i b ? 13405-234 figure 34. input bias current (i b ) vs. temperature, v sy = 4.5 v 1000 0.001 0.01 0.1 1 10 100 010 30 20 40 50 60 70 80 90 100 110 120 130 i b (fa) temperature (c) v sy = 10v v cm = v sy /2 rh < 10% ?40c to +85c limit ?40c to +125c limit 13405-235 i b + i b ? figure 35. input bias current (i b ) vs. temperature, v sy = 10 v 1000 0.001 0.01 0.1 1 10 100 010 30 20 40 50 60 70 80 90 100 110 120 130 i b (fa) temperature (c) v sy = 16v v cm = v sy /2 rh < 10% ?40c to +85c limit ?40c to +125c limit 13405-236 i b + i b ? figure 36. input bias current (i b ) vs. temperature, v sy = 16 v 120 100 80 60 40 20 0 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 number of amplifiers i b ? (fa) v sy = 10v v cm = v sy /2 590 channels t a = 125c x = ?40.69fa = 24.54fa 13405-019 figure 37. inverting input bias current histogram, t a = 125c, v sy = 10 v 120 100 80 60 40 20 0 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 number of amplifiers i b + (fa) v sy = 10v v cm = v sy /2 590 channels t a = 125c x = ?74.59fa = 23.66fa 13405-020 figure 38. noninverting input bias current histogram, t a = 125c, v sy = 10 v 160 120 140 100 80 60 40 20 0 ?150 ?120 ?90 ?60 ?30 0 30 60 90 120 150 number of amplifiers i os (fa) v sy = 10v v cm = v sy /2 590 channels t a = 125c x = 33.9fa = 17.9fa 13405-239 figure 39. input offset current histogram
data sheet ada4530-1 rev. a | page 17 of 50 10 0.0001 0.001 0.01 0.1 1 0.01 0.1 1 10 100 output voltage low (v ol ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 4.5v 13405-037 figure 40. output voltage low (v ol ) to supply rail vs. load current (i load ), v sy = 4.5 v 10 0.0001 0.001 0.01 0.1 1 0.01 0.1 1 10 100 output voltage low (v ol ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 10v 13405-038 figure 41 output voltage low (v ol ) to supply rail vs. load current (i load ), v sy = 10 v 10 0.0001 0.001 0.01 0.1 1 0.01 0.1 1 10 100 output voltage low (v ol ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 16v 13405-039 figure 42. output voltage low (v ol ) to supply rail vs. load current (i load ), v sy = 16 v 10 0.001 0.01 0.1 1 0.01 0.1 1 10 100 output voltage high (v oh ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 4.5v 13405-040 figure 43. output voltage high (v oh ) to supply rail vs. load current (i load ), v sy = 4.5 v 10 0.001 0.01 0.1 1 0.01 0.1 1 10 100 output voltage high (v oh ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 10v 13405-041 figure 44. output voltage high (v oh ) to supply rail vs. load current (i load ), v sy = 10 v 10 0.001 0.01 0.1 1 0.01 0.1 1 10 100 output voltage high (v oh ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 16v 13405-042 figure 45. output voltage high (v oh ) to supply rail vs. load current (i load ), v sy = 16 v
ada4530-1 data sheet rev. a | page 18 of 50 100 90 80 70 60 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 temperature (c) output voltage low (v ol ) to supply rail (mv) v sy = 4.5v r l = 2k ? r l = 10k ? 13405-043 figure 46. output voltage low (v ol ) to supply rail vs. temperature, v sy = 4.5 v 225 200 175 125 150 75 100 25 50 0 temperature (c) ?50 ?25 0 25 50 75 100 125 output voltage low (v ol ) to supply rail (mv) v sy = 10v r l = 2k ? r l = 10k ? 13405-044 figure 47. output voltage low (v ol ) to supply rail vs. temperature, v sy = 10 v 360 330 300 270 240 210 180 150 120 90 60 30 0 ?50 ?25 0 25 50 75 100 125 temperature (c) output voltage low (v ol ) to supply rail (mv) v sy = 16v r l = 2k ? r l = 10k ? 13405-045 figure 48. output voltage low (v ol ) to supply rail vs. temperature, v sy = 16 v 100 90 80 70 60 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 temperature (c) output voltage high (v oh ) to supply rail (mv) v sy = 4.5v r l = 2k ? r l = 10k ? 13405-046 figure 49. output voltage high (v oh ) to supply rail vs. temperature, v sy = 4.5 v 225 200 175 125 150 75 100 25 50 0 temperature (c) ?50 ?25 0 25 50 75 100 125 v sy = 10v output voltage high (v oh ) to supply rail (mv) r l = 2k ? r l = 10k ? 13405-047 figure 50. output voltage high (v oh ) to supply rail vs. temperature, v sy = 10 v 360 330 300 270 240 210 180 150 120 90 60 30 0 ?50 ?25 0 25 50 75 100 125 temperature (c) output voltage high (v oh ) to supply rail (mv) v sy = 16v r l = 2k ? r l = 10k ? 13405-048 figure 51. output voltage high (v oh ) to supply rail vs. temperature, v sy = 16 v
data sheet ada4530-1 rev. a | page 19 of 50 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 4 8 11 16 2 6 10 14 i sy per amplifier (ma) supply voltage (v) ?40c +25c +85c +125c v cm = v sy /2 13405-049 figure 52. supply current (i sy ) per amplifier vs. supply voltage (v sy ) 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 temperature (c) ?50 ?25 0 25 50 75 100 125 i sy per amplifier (ma) v cm = v sy /2 4.5v 10v 16v 13405-050 figure 53. supply current (i sy ) per amplifier vs. temperature 0 ?200 ?180 ?140 ?120 ?60 ?160 ?100 ?80 ?40 ?20 01 3 2 45678910 small signal psrr (db) v cm (v) v sy = 10v ? v cm = 400mv preferred input voltage range psrr? psrr+ 13405-254 figure 54. small signal psrr vs. common-mode voltage (v cm )
ada4530-1 data sheet rev. a | page 20 of 50 main amplifier, ac performance v sy = 4.5 v to 16 v, data taken at v sy = 10 v, t a = 25c, unless otherwise noted. 120 100 80 60 40 20 0 ?20 ?40 ?60 10k 100k 1m 10m open-loop gain (db) frequency (hz) 120 100 80 60 40 20 0 ?20 ?40 ?60 phase margin (degrees) 10pf 10pf 100pf 100pf v sy = 10v r l = 10k ? 13405-055 figure 55. open-loop gain and phase margin vs. frequency 10k 100k 10m 1m frequency (hz) 100 90 80 70 60 50 40 30 20 10 0 cmrr (db) v sy = 10v v cm = v sy /2 r l = 10k ? c l = 10pf 13405-056 figure 56. cmrr vs. frequency 10k 100k 10m 1m 60 50 40 30 20 10 0 psrr (db) frequency (hz) pssr+ pssr? v sy = 10v v cm = v sy /2 r l = 10k ? c l = 10pf 13405-057 figure 57. psrr vs. frequency 60 ?20 0 ?10 10 30 50 20 40 1k 10k 100k 1m 10m closed-loop gain (db) frequency (hz) v sy = 10v r l = 10k ? c l = 10pf a v = +1 a v = +10 a v = +100 13405-058 figure 58. closed-loop gain vs. frequency 10k 0.0001 0.01 0.001 0.1 10 1k 1 100 100 1k 10k 100k 1m 10m closed-loop output impedance ( ? ) frequency (hz) a v = +10 a v = +100 a v = +1 v sy = 10v v cm = v sy /2 13405-059 figure 59. closed-loop outp ut impedance vs. frequency 60 50 40 30 20 10 0 0 30 60 90 120 150 180 210 240 270 overshoot (%) load capacitance (pf) v sy = 10v v in = 100mv p-p a v = +1 r l = 10k ? os? os+ 13405-060 figure 60. small signal overshoot vs. load capacitance
data sheet ada4530-1 rev. a | page 21 of 50 80 ?80 ?40 20 60 0 ?60 ?20 40 voltage (mv) time (2s/div) v sy = 4.5v v in = 100mv p-p a v = +1 r l = 10k ? c l = 10pf r s = 1k ? 13405-061 figure 61. small signal transient response, v sy = 4.5 v 80 ?80 ?40 20 60 0 ?60 ?20 40 voltage (mv) time (2s/div) v sy = 10v v in = 100mv p-p a v = +1 r l = 10k ? c l = 10pf r s = 1k ? 13405-062 figure 62. small signal transient response, v sy = 10 v 80 ?80 ?40 20 60 0 ?60 ?20 40 voltage (mv) time (2s/div) v sy = 16v v in = 100mv p-p a v = +1 r l = 10k ? c l = 10pf r s = 1k ? 13405-063 figure 63. small signal transient response, v sy = 16 v 1.0 ?2.5 ?2.0 ?1.5 ?0.5 0.5 ?1.0 0 voltage (v) v sy = 4.5v v in = 2.75v p-p a v = +1 r l = 10k ? c l = 10pf r s = 1k ? time (2s/div) 13405-064 figure 64. large signal transient response, v sy = 4.5 v 6 ?6 ?4 0 4 ?2 2 voltage (v) v sy = 10v v in = 8.25v p-p a v = +1 r l = 10k ? c l = 10pf r s = 1k ? time (5s/div) 13405-065 figure 65. large signal transient response, v sy = 10 v 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 voltage (v) v sy = 16v v in = 14.25v p-p a v = +1 r l = 10k ? c l = 10pf r s = 1k ? time (20s/div) 13405-066 figure 66. large signal transient response, v sy = 16 v
ada4530-1 data sheet rev. a | page 22 of 50 v out ?1.4 input voltage (v) 0.2 0 ?1.0 ?0.4 ?0.6 ?1.2 ?0.8 ?0.2 time (2s/div) 7 6 5 3 4 1 2 0 ?1 output voltage (v) v sy = 4.5v v in = 450mv a v = ?10 r l = 10k ? c l = 10pf v in 13405-067 figure 67. positive overload recovery, v sy = 4.5 v 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 ?1.6 ?1.8 ?2.0 ?2.2 ?2.4 ?2.6 ?2.8 ?3.0 ?3.2 input voltage (v) output voltage (v) v sy = 10v v in = 900mv a v = ?10 r l = 10k ? c l = 10pf 16 14 15 12 13 8 9 10 11 3 2 4 5 6 7 1 0 ?1 v in v out time (2s/div) 13405-068 figure 68. positive overload recovery, v sy = 10 v 1 ?8 ?6 ?3 ?1 0 ?4 ?7 ?5 ?2 input voltage (v) output voltage (v) time (2s/div) 24 21 18 15 9 0 3 6 12 ?3 v sy = 16v v in = 1.5v a v = ?10 r l = 10k ? c l = 10pf v in v out 13405-069 figure 69. positive overload recovery, v sy = 16 v 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 input voltage (v) output voltage (v) time (2s/div) v sy = 4.5v v in = 400mv a v = ?10 r l = 10k ? c l = 10pf v in v out 2.5 2.0 1.5 1.0 ?0.5 ?2.0 ?1.5 ?1.0 0 0.5 ?2.5 13405-070 figure 70. negative overload recovery, v sy = 4.5 v 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 ?1.6 input voltage (v) output voltage (v) time (2s/div) v sy = 10v v in = 900mv a v = ?10 r l = 10k ? c l = 10pf v in v out 7 5 3 1 ?1 ?5 ?3 ?7 13405-071 figure 71. negative overload recovery, v sy = 10 v 2 1 0 ?1 ?2 ?3 ?4 input voltage (v) output voltage (v) time (2s/div) v sy = 16v v in = 1.5v a v = ?10 r l = 10k ? c l = 10pf v in v out 12 8 4 0 ?4 ?8 ?12 13405-072 figure 72. negative overload recovery, v sy = 16 v
data sheet ada4530-1 rev. a | page 23 of 50 input voltages (250mv/div) output voltage (5mv/div) time (1s/div) v sy = 4.5v dut a v = ?1 r l = 10k ? c l = 10pf error band post gain = 20 input output 13405-273 figure 73. negative settling time to 0.1%, v sy = 4.5 v input voltages (250mv/div) time (1s/div) v sy = 10v dut a v = ?1 r l = 10k ? c l = 10pf error band post gain = 20 output voltage (5mv/div) input output 13405-274 figure 74. negative settling time to 0.1%, v sy = 10 v input voltages (250mv/div) time (1s/div) v sy = 16v dut a v = ?1 r l = 10k ? c l = 10pf error band post gain = 20 output voltage (5mv/div) input output 13405-275 figure 75. negative settling time to 0.1%, v sy = 16 v time (1s/div) v sy = 4.5v dut a v = ?1 r l = 10k ? c l = 10pf error band post gain = 20 output voltage (5mv/div) input output 13405-276 input voltages (250mv/div) figure 76. positive settling time to 0.1%, v sy = 4.5 v time (1s/div) v sy = 10v dut a v = ?1 r l = 10k ? c l = 10pf error band post gain = 20 output voltage (5mv/div) input output 13405-277 input voltages (250mv/div) figure 77. positive settling time to 0.1%, v sy = 10 v time (1s/div) v sy = 16v dut a v = ?1 r l = 10k ? c l = 10pf error band post gain = 20 output voltage (5mv/div) input output 13405-278 input voltages (250mv/div) figure 78. positive settling time to 0.1%, v sy = 16 v
ada4530-1 data sheet rev. a | page 24 of 50 0.1 0.001 0.01 10 100 10k 1k 100k thd + n (%) frequency (hz) 90khz low-pass filter 500khz low-pass filter v sy = 4.5v a v = +1 r l = 10k ? v in = 0.5v rms 13405-279 figure 79. thd + n vs. frequency, v sy = 4.5 v 0.1 0.001 0.01 10 100 10k 1k 100k thd + n (%) frequency (hz) 90khz low-pass filter 500khz low-pass filter v sy = 10v a v = +1 r l = 10k ? v in = 2v rms 13405-280 figure 80. thd + n vs. frequency, v sy = 10 v 1 0.1 0.001 0.01 10 100 10k 1k 100k thd + n (%) frequency (hz) 90khz low-pass filter 500khz low-pass filter v sy = 16v a v = +1 r l = 10k ? v in = 4.5v rms 13405-281 figure 81. thd + n vs. frequency, v sy = 16 v 10 1 0.1 0.001 0.01 0.001 0.01 0.1 1 thd + n (%) amplitude (v rms) 90khz low-pass filter 500khz low-pass filter v sy = 4.5v a v = +1 r l = 10k ? f = 1khz 13405-282 figure 82. thd + n vs. amplitude, v sy = 4.5 v 10 1 0.1 0.0001 0.001 0.01 0.001 0.01 0.1 10 1 thd + n (%) amplitude (v rms) 90khz low-pass filter 500khz low-pass filter v sy = 10v a v = +1 r l = 10k ? f = 1khz 13405-283 figure 83. thd + n vs. amplitude, v sy = 10 v 10 1 0.1 0.001 0.01 0.001 0.01 0.1 10 1 thd + n (%) amplitude (v rms) 90khz low-pass filter 500khz low-pass filter v sy = 16v a v = +1 r l = 10k ? f = 1khz 13405-284 figure 84. thd + n vs. amplitude, v sy = 16 v
data sheet ada4530-1 rev. a | page 25 of 50 1000 100 10 1 0.1 100m 10m1m 100k 10k1k10010 1 voltage noise density (nv/ ? c l = 10pf 13405-285 figure 85. voltage noise density, v sy = 10 v 3 1 ?1 2 0 ?2 ?3 input referred voltage (v) time (1s/div) v sy = 10v noise = 4v p-p 13405-286 figure 86. 0.1 hz to 10 hz noise
ada4530-1 data sheet rev. a | page 26 of 50 guard amplifier t a = 25c, unless otherwise noted. 120 100 80 60 40 20 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 number of amplifiers v os (v) v sy = 4.5v v cm = v sy /2 590 channels t a = 25c x = ?3.68v = 12.35v 13405-091 figure 87. input offset voltage distribution, v sy = 4.5 v 120 100 80 60 40 20 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 number of amplifiers v os (v) v sy = 10v v cm = v sy /2 590 channels t a = 25c x = ?3.8v = 12.4v 13405-092 figure 88. input offset voltage distribution, v sy = 10 v 120 100 80 60 40 20 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 number of amplifiers v os (v) v sy = 16v v cm = v sy /2 590 channels t a = 25c x = ?3.86v = 12.2v 13405-093 figure 89. input offset voltage distribution, v sy = 16 v 100 50 ?50 0 ?100 ?150 ?50 ?25 0 25 50 75 100 125 v os (v) temperature (c) v sy = 4.5v v cm = v sy /2 574 channels 13405-094 figure 90. input offset voltage (v os ) vs. temperature, v sy = 4.5 v 100 50 ?50 0 ?100 ?150 ?50 ?25 0 25 50 75 100 125 v os (v) temperature (c) v sy = 10v v cm = v sy /2 574 channels 13405-095 figure 91. input offset voltage (v os ) vs. temperature, v sy = 10 v 100 50 ?50 0 ?100 ?150 ?50 ?25 0 25 50 75 100 125 v os (v) temperature (c) v sy = 16v v cm = v sy /2 574 channels 13405-096 figure 92. input offset voltage (v os ) vs. temperature, v sy = 16 v
data sheet ada4530-1 rev. a | page 27 of 50 tcv os (v/c) 120 100 80 60 40 20 0 number of amplifiers ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 v sy = 4.5v v cm = v sy /2 574 channels ?40c t a 0c x = 0.26v/c = 1.14v/c 13405-097 figure 93. input offset voltage drift distribution, ?40c t a 0c, v sy = 4.5 v tcv os (v/c) 120 100 80 60 40 20 0 number of amplifiers ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 v sy = 10v v cm = v sy /2 574 channels ?40c t a 0c x = 0.26v/c = 1.14v/c 13405-098 figure 94. input offset voltage drift distribution, ?40c t a 0c, v sy = 10 v tcv os (v/c) 120 100 80 60 40 20 0 number of amplifiers ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 v sy = 16v v cm = v sy /2 574 channels ?40c t a 0c x = 0.27v/c = 1.14v/c 13405-099 figure 95. input offset voltage drift distribution, ?40c t a 0c, v sy = 16 v 160 0 40 100 140 80 20 60 120 ?1.0 ?0.6 ?0.2 0.2 0.6 ?0.8 ?0.4 0 0.4 0.8 1.0 tcv os (v/c) number of amplifiers v sy = 4.5v v cm = v sy /2 574 channels 0c t a 125c x = 0.014v/c = 0.168v/c 13405-100 figure 96. input offset voltage drift distribution, 0c t a 125c, v sy = 4.5 v 160 0 40 100 140 80 20 60 120 ?1.0 ?0.6 ?0.2 0.2 0.6 ?0.8 ?0.4 0 0.4 0.8 1.0 tcv os (v/c) number of amplifiers v sy = 10v v cm = v sy /2 574 channels 0c t a 125c x = 0.017v/c = 0.168v/c 13405-101 figure 97. input offset voltage drift distribution, 0c t a 125c, v sy = 10 v 160 0 40 100 140 80 20 60 120 ?1.0 ?0.6 ?0.2 0.2 0.6 ?0.8 ?0.4 0 0.4 0.8 1.0 tcv os (v/c) number of amplifiers v sy = 16v v cm = v sy /2 574 channels 0c t a 125c x = 0.02v/c = 0.168v/c 13405-102 figure 98. input offset voltage drift distribution, 0c t a 125c, v sy = 16 v
ada4530-1 data sheet rev. a | page 28 of 50 theory of operation the ada4530-1 is an operational amplifier specifically designed to interface with the extremely high impedance sensors used in electrometer applications. a mosfet input stage eliminates the gate leakage currents associated with legacy junction gate field effect transistor (jfet) electrometers. the ada4530-1 achieves extremely low input bias currents while simultaneously providing robust protection against esd damage. a unique esd diode structure provides protection while also allowing the diodes to be guarded to minimize leakage currents to the input pins. the ada4530-1 integrates the precision buffer used to guard internal esd diode leakage paths. the output of this guard buffer is also connected to external pins to allow the user to guard external components against leakage currents. the input bias current is determined by the accuracy of the guard voltage applied across the esd diodes. the offset voltages of the amplifier and guard buffer set the accuracy of the guard voltage and, therefore, the input bias current. the ada4530-1 uses analog devices, inc., digitrim? technology to achieve its superior performance. digitrim is used to trim the offset voltage of the amplifier and guard buffer to reject changes in the common-mode voltage, power supply voltage, and temperature. this technique significantly improves v os , cmrr, psrr, and tcv os specifications. figure 99 shows the simplified schematic of the ada4530-1 . the amplifier uses a three-stage architecture with a fully differential input stage to achieve excellent dc performance specifications. esd structure the input esd structure consists of diode d1 to diode d6. the noninverting input is coupled to the guard pins (grd) by the d1 and d2 antiparallel diodes. the inverting input is coupled to the guard pins by the d3 and d4 antiparallel diodes. the guard pins are connected to the power supplies through diode d5 and diode d6. during esd events, the transient current flows from the input pins through one of the antiparallel diodes and harmlessly into the supplies through one of the power supply diodes. during normal operation, the guard buffer (buf1) forces the voltage across the antiparallel diodes to 0 v. resistor r1 shields the guard buffer from potentially large capacitances connected to the guard pins. its value is nominally 1 k. input stage the input stage comprises a pmos differential pair (m1, m2), folded cascode transistors (m5 to m12), and current source i1. the ada4530-1 achieves its high performance specifications by using low voltage mos devices for its differential inputs. these low voltage mos devices offer better 1/f noise and bandwidth per unit current compared to high voltage devices. the input stage is isolated from the high system voltages with proprietary protection circuitry. this regulation circuitry protects the input devices from the high supply voltages in which the amplifier can operate. the proprietary high voltage protection circuitry in the ada4530-1 operates in such a way that it minimizes the common-mode voltage changes seen by the amplifier input stage for most of the input common-mode range. this circuitry results in excellent disturbance rejection when operating in this preferred input common-mode range. the performance benefits of operating within this preferred range are shown in the v os vs. v cm graphs (see figure 16 to figure 18), the small signal cmrr vs. v cm graph (see figure 21), and the small signal psrr vs. v cm graph (see figure 54). these input devices are protected from large differential input voltages by the antiparallel esd diodes (d1 to d4). the diodes can conduct significant current when the differential voltage exceeds 700 mv. the user must ensure that the current flowing into the input pins is limited to the absolute maximum of 10 ma. v? v + +in ?in grd grd d1 d5 d6 d2 d3 d4 m1 m2 m11 m7 m12 m10 m8 m6 m5 m9 m15 m16 m14 m13 m21 m19 m20 m18 m17 m22 r1 buf1 high voltage protection high voltage protection i1 i2 m3 m4 v1 c1 c2 c3 out 13405-299 figure 99. simplified schematic
data sheet ada4530-1 rev. a | page 29 of 50 gain stage the second stage of the amplifier comprises an nmos differen- tial pair (m3, m4) and folded cascode transistors (m13 to m20). the amplifier features nested miller compensation (c1 to c3). output stage the ada4530-1 features a complementary common-source output stage consisting of the m21 and m22 transistors. these transistors are configured in a class ab topology and are biased by the voltage source, v1. this topology allows the output voltage to be within tens of millivolts of the supply rails, achieving a rail-to-rail output swing. the output voltage is limited by the output impedance of the transistors. the output voltage swing is a function of the load current and can be estimated using the output voltage to the supply rail vs. load current graphs (see figure 40 to figure 45). guard buffer the guard buffer (buf1) is a unity-gain amplifier that creates a low impedance replica of the input common-mode voltage. the buffer input is connected to the noninverting input (in+). the noninverting input voltage is approximately equal to the input common-mode voltage when the main amplifier feedback loop is settled. the guard buffer uses a three-stage architecture similar to that of the amplifier. the guard buffer uses a rail-to-rail output stage that allows the guard voltage to swing within 100 mv of the supply rails. because the guard buffer output follows the input common-mode voltage, this output swing limits the effectiveness of the guard buffer at low input common-mode voltages. this limit can be seen as a significant increase in input bias current at low common-mode voltages in the input bias current vs. common-mode voltage graphs (see figure 22 to figure 33). for this reason, it is not recommended to operate the circuit with an input common-mode voltage of less than 100 mv from the v? supply rail. the guard buffer output voltage can be degraded from excessive loading. the 1 k output resistance adds 1 v of guard voltage error per 1 na of load current. it is possible to drive the guard offset voltage out of its specifications with a few tens of nano- amperes of load current. for this reason, it is not recommended to drive anything except insulation resistance (see the insulation resistance and guarding section) with the guard buffer. if more drive strength is needed, the guard voltage can be buffered with a low offset, low input bias current op amp such as the ada4661-2 .
ada4530-1 data sheet rev. a | page 30 of 50 applications information the ada4530-1 is a single, electrometer grade, cmos operational amplifier with femtoampere input bias current and ultralow offset voltage. it operates over a wide supply voltage range of 4.5 v (or 2.25 v dual supply) to 16 v (or 8 v dual supply). it is a single-supply amplifier, where its input voltage range includes the lower supply rail and has a rail-to-rail output. the ada4530-1 also achieves a low offset voltage of 40 v maximum and offset voltage drift of 0.5 v/c maximum. the ada4530-1 has ultralow input bias currents that are production tested at 25c and 125c to ensure that the device meets its performance goals in a system application. an integrated guard buffer is provided to minimize input pin leakage in a printed circuit board (pcb) design, minimize board component count, and enable ease of system design. the guard buffer output pins are also strategically placed next to the input pins to enable easy routing of the guard ring and to prevent coupling between the inputs, power supplies, and the output pin. the ada4530-1 is suited for applications requiring very low input bias current and low offset voltage, including, but not limited to, preamplifier applications, for a wide variety of current output transducers (photodiodes, photomultiplier tubes), spectrometry, chromatography, and high impedance buffering for chemical sensors. input protection when either input of the ada4530-1 exceeds one of the supply rails by more than 300 mv, the input esd diodes become forward-biased and large amounts of current begin to flow through them. without current limiting, this excessive fault current causes permanent damage to the device. if the inputs are expected to be subject to overvoltage conditions, insert a resistor in series with each input to limit the input current to 10 ma maximum. however, consider the resistor thermal noise effect on the entire circuit. single-supply and rail-to-rail output the ada4530-1 is a single supply amplifier with an input voltage range (ivr) from v? to v+ ? 1.5 v. the amplifier has a small keep alive input stage that allows it to function properly when the input common-mode voltage is greater than the specified ivr. this feature allows the ada4530-1 to start up and recover quickly in certain types of circuits where the ivr is violated at power-up. the ac and dc performance of this keep alive stage is poor; do not rely upon this keep alive stage for normal use. figure 100 shows the input and output waveforms of the ada4530-1 configured as a unity-gain buffer with a supply voltage of 8 v. the output tracks the input voltage over the entire range until the output voltage is clamped at its maximum output swing. note that the amplifier still operates even when the signal is outside the specified input voltage range (?8 v ivr +6.5 v); this is due to the keep alive stage. additionally, it does not phase reverse. it is not recommended to apply an input voltage that is outside of the input voltage range. 10 2 ?2 6 4 8 0 ?6 ?4 ?8 ?10 voltage (v) time (200s/div) v sy = 8v v in = 8.3v a v = +1 r l = 10k ? c l = 10pf v in v out 13405-300 figure 100. no phase reversal capacitive load stability the ada4530-1 can safely drive capacitive loads of up to 250 pf in any configuration. as with most amplifiers, driving larger capacitive loads than specified may cause excessive overshoot and ringing, or even oscillation. a heavy capacitive load reduces phase margin and causes the amplifier frequency response to peak. peaking corresponds to overshooting or ringing in the time domain. therefore, it is recommended that external compensation be used if the ada4530-1 must drive a load exceeding 250 pf. this compensation is particularly important in the unity-gain configuration, which is the worst case for stability. a quick and easy way to stabilize the op amp for capacitive load drive is by adding a series resistor, r iso , between the amplifier output terminal and the load capacitance, as shown in figure 101. r iso isolates the amplifier output and feedback network from the capacitive load. however, with this compensation scheme, the output impedance as seen by the load increases, and this reduces gain accuracy. ?v sy v in +v sy v out c l ada4530-1 r iso 13405-201 figure 101. stability compensation with isolating resistor, r iso
data sheet ada4530-1 rev. a | page 31 of 50 figure 102 shows the phase margin of the ada4530-1 with different values of output isolating resistors and capacitive loads. figure 103 shows the frequency response with 1 nf capacitive load and different isolating resistors. 80 60 50 70 40 phase margin (degrees) v sy = 10v a v = +1 r iso = 301 ? r iso = 499 ? r iso = 732 ? 100 1000 10000 capacitive load (pf) 13405-302 figure 102. phase margin vs. load capacitance with various output isolating resistors 100 40 0 80 20 ?20 60 ?40 100 40 0 80 20 ?20 60 ?40 gain (db) phase (degrees) v sy = 10v a v = +1 c l = 1nf phase gain 1k 100k 10k 1m 10m frequency (hz) 13405-303 gain (r iso = 0 ? ) gain (r iso = 301 ? ) gain (r iso = 732 ? ) phase (r iso = 0 ? ) phase (r iso = 301 ? ) phase (r iso = 732 ? ) figure 103. frequency response with c l = 1 nf and various isolating resistors emi rejection ratio circuit performance is often adversely affected by high frequency electromagnetic interference (emi). when the signal strength is low and transmission lines are long, an op amp must accurately amplify the input signals. however, all op amp pinsthe noninverting input, inverting input, positive supply, negative supply, and output pinsare susceptible to emi signals. these high frequency signals are coupled into an op amp by various means, such as conduction, near field radiation, or far field radiation. for example, wires and pcb traces can act as antennas and pick up high frequency emi signals. amplifiers do not amplify emi or rf signals due to their relatively low bandwidth. however, due to the nonlinearities of the input devices, op amps can rectify these out of band signals. when these high frequency signals are rectified, they appear as a dc offset at the output. to describe the ability of the ada4530-1 to perform as intended in the presence of electromagnetic energy, the electromagnetic interference rejection ratio (emirr) of the noninverting pin is specified in table 1, table 2, and table 3 of the specifications section. a mathematical method of measuring emirr is defined as follows: emirr = 20log( v in_peak /v os ) figure 104 shows the typical emirr vs. frequency performance for each of the specified supply voltages. 120 100 70 20 40 90 60 30 110 80 50 10m 100m 1g 10g emirr (db) frequency (hz) v sy = 4.5v v sy = 10v v sy = 16v v sy = 4.5v to 16v 13405-304 figure 104. emirr vs. frequency
ada4530-1 data sheet rev. a | page 32 of 50 high impedance measurements the ada4530-1 is designed to maximize the performance of very high impedance circuits. its performance advantages make it useful for circuit impedances ranging from 100 m to over 10 t. measurements of high impedance circuits are subject to a number of error sources. general information about making measurements from high resistance sources can be found in the low level measurements handbook , sixth edition (keithley instruments, inc., 2004). the ada4530-1 is typically used in two kinds of circuits: a buffer and a tia. buffer circuits are useful for measuring voltage output sensors with high output resistance. some example sensors include ph probes and reference electrodes (re) in coulometry control loops. tia circuits are useful for converting the signal from a current output sensor to an output voltage. some example sensors include photodiodes and ion chambers. the following sections describe some of the most important error sources when using the ada4530-1 in these circuits. simplified models with error sources are provided for the buffer (see figure 105) and the tia (see figure 106). the buffer circuit models the voltage output sensor as a voltage source (v src ) with an output resistance (r src ). the voltage on the a terminal is sensed by pin 1 of the ada4530-1 in a noninverting gain configuration (or a unity-gain configuration). the b terminal is driven to a suitable reference voltage (signal ground in this case). if all errors sources are ignored, the output of the circuit is as follows: ? ? ? ? ? ? ? ? ?? s f src out r r vv 1 ada4530-1 r f r src v src r s i b + r in v os 1 8 6 v out b a v oltage sensor 13405-310 r shunt +in out ?in figure 105. voltage buffer circuit the tia circuit models the current output sensor as a current source (i src ) with a shunt resistance (r src ). the current from the a terminal is connected to the inverting input pin of the ada4530-1 and the feedback resistor (r f ). the b terminal and the noninverting input of the amplifier are driven to a suitable reference voltage (signal ground in this case). the negative feedback of the circuit suppresses any voltage changes at the a terminal. this suppression is accomplished by forcing all current through the feedback resistor. if all error sources are ignored, the output of the circuit is as follows: v out = i src r f ada4530-1 r src i src i b ? r in r shunt v os 8 1 6 v out b a current sensor r f v + i rf 13405-311 figure 106. transimpedance amplifier circuit input bias current the input bias current of the amplifier is a major error source in high impedance electrometer circuits. like other semiconductor amplifiers, the input bias current of the ada4530-1 has an exponential dependence on temperature. the input bias current of the ada4530-1 increases by a factor of 2.5 for every 10c increase in temperature. refer to the input bias current vs. temperature graphs (see figure 34 to figure 36) for typical temperature performance. notice that the exponen- tial diode currents cease to be the dominate contributor to the input bias current at temperatures below 60c to 70c. the residual 100 aa to 200 aa (aa = 10 ?18 a) bias currents are dominated by other leakage paths that are highly sensitive to environmental conditions. these vanishingly small bias currents require highly controlled laboratory conditions to measure. most practical applications are dominated by other errors, and the ada4530-1 input bias current can be considered to be zero for temperatures less than 70c. the input bias current of the ada4530-1 can only be guaranteed to 20 fa due to the measurement limitations of a production environment even though the achievable input bias currents are more than an order of magnitude lower. the input bias current affects the buffer circuit by loading down the voltage sensor. the input bias current is forced to flow through the output resistance of the sensor, which creates an error voltage. v err = i b+ (r src ) the magnitude of this voltage error can be significant with very high impedance sensors operating at high temperature. for example, the input bias current can generate a maximum voltage error of 25 mv from a 100 g sensor operating at 125c. the input bias current affects the tia circuit by summing together with the sensor current. both of these currents flow through the feedback resistor to generate the output voltage as follows: v out = ( i src + i b? ) r f
data sheet ada4530-1 rev. a | page 33 of 50 the magnitude of the input bias current limits how small of a signal current may be resolved accurately. for example, if the acceptable error level is 10%, the minimum measurable signal current is 2.25 pa for a circuit operating at 125c. i src = i b? (1/ err C 1) where err is the error level. ? ? ? ? ? ? ? ? 1 1.0 1 fa250pa25.2 input resistance the input resistance of the amplifier is another error source that must be considered. input resistance typically has two compo- nents: differential and common mode. the differential input resistance is suppressed by the negative feedback of the circuit. the ada4530-1 has enough gain that the differential input resistance is much too large to measure. the common-mode input resistance (hereafter referred to as input resistance) is a more important error source. the input resistance is equal to the change in input bias current relative to the change in input voltage. this change is not caused by a physical resistance inside the ada4530-1 ; it is the result of a complex relationship between the accuracy of the guard voltage across the esd structures and the input common-mode voltage; that is, the input resistance changes with common mode voltage. it is also possible for the input resistance to be negative. negative input resistance means the input bias current decreases as the common-mode voltage increases. the input resistance, r in , can be approximated by calculating the slope of the input bias current vs. common-mode voltage graphs (see figure 22 to figure 33). for example, the noninverting input resistance can be calculated at 125c from figure 32. note that the input bias current changes by approximately 20 fa for common-mode voltages from 4 v to 6 v. ? ? ? ? b cm in i v r t 100 fa20 v2 ?? in r the slope of the curves in the input bias current vs. common- mode voltage graphs increases rapidly outside the preferred common-mode range (see figure 22 to figure 33). the input resistance drops rapidly outside this range. this drop in input resistance must be considered before operating these circuits with input voltages close to the v? power supply. like the input bias current, the input resistance has a strong temperature dependence. at lower temperatures, the amplifier input resistance is so high that it is dominated by other error sources. it is important to recognize the limitations of calculating input resistance at lower temperatures. measurement uncertain- ties make it difficult to accurately calculate the i b term. consider the 85c input bias current vs. common-mode voltage graphs (see figure 22 to figure 27); the measurement uncertainties are equal to a few fa, which is the same magnitude as the input bias current itself. these uncertainties make it impossible to calcu- late input resistances higher than a few hundred teraohms. the input resistance affects the buffer circuit by loading down the voltage sensor. this resistance acts as a voltage divider so the voltage measured by the amplifier is some fraction of the unloaded voltage of the sensor. this voltage drop is calculated as follows: src in in srca rr r vv ? ? consider the previous example of a 100 g sensor operating at 125c. the 100 t input resistance causes the measured voltage to equal 99.9% of the actual voltage, a 0.1% gain error. the input resistance has much less of an effect on the tia circuit. the input common-mode voltage does not change in this circuit; therefore, the error created is vanishingly small. the input resistance affects the noise gain of the circuit, which changes the input offset voltage error (see the photodiode interface section for more information). input offset voltage the input offset voltage of the amplifier affects the buffer circuit by adding directly to the voltage output of the sensor. this error is typically much smaller than other errors. the input offset voltage affects the tia circuit in a different manner. the burden voltage of the tia is equal to the input offset voltage. this burden voltage appears between the a and b terminals. an error current is created by applying this burden voltage across the sensor shunt resistance. for sensors with low output resistances such as photodiodes, this error can be significant. consider a sensor with a 1 g output resistance. the 50 v maximum offset voltage of the ada4530-1 creates a 50 fa error current. insulation resistance the ada4530-1 has such low input bias current and such high input resistance that the insulation resistance of the materials that are used to construct the circuit is often the largest error source. any insulators with finite resistance that come in contact with the high impedance conductor contribute to the error current. some examples include the printed circuit board (pcb) laminate material, cable, and connector insulation. the physical insulation resistance is distributed across the entire contact surface of the high impedance conductor, and it may end at several different conductors at different potentials. it is useful to make a simple model where all of these resistance paths are lumped into a single resistor. this lumped element is shown as r shunt in the voltage buffer circuit (see figure 105). the insulation resistance affects the buffer circuit in the same way as the amplifier input resistance. this resistance acts as a voltage divider so that the voltage measured by the amplifier is some fraction of the unloaded voltage of the sensor. this error is significant because it is very difficult to maintain high
ada4530-1 data sheet rev. a | page 34 of 50 insulation resistance values in glass epoxy (such as fr-4) pcb materials. resistance values of 10 t to 100 t are achievable. a 10 t insulation resistance creates a 1% error with the 100 g sensor used in previous examples. insulation resistance does not have an exponential temperature dependence like the amplifier errors previously discussed in the input bias current section and the input resistance section, which makes insulation resistance the dominate error source at lower temperatures (less than 70c). the effect on the insulation resistance on the tia circuit depends on the leakage path. the insulation resistance between the a terminal and b terminal of the current sensor affects the circuit in the same way as the amplifier input resistance. this error is extremely small because the voltage across the insulation is equal to the offset voltage of the amplifier. a much more significant error is created from insulation paths to conductors with significantly different potentials. this type of leakage path is shown as lumped element, r shunt , in the tia circuit (see figure 106). in this example, the leakage path is created from the positive supply voltage (v+) to the a terminal. if the positive supply voltage is 5 v relative to signal ground, 500 fa flows through the insulation resistance of 10 t. this large error dominates the amplifier input bias current and input resistance errors over the entire temperature range. leakage paths to high voltages can also affect the buffer circuit with equally ruinous results. guarding high source impedances and low error requirements can create insulation resistance requirements that are unrealistically high. fortunately, a technique called guarding can reduce these requirements to a reasonable level. the concept of guarding is to surround the high impedance conductor with another conductor (guard) that is driven to the same voltage potential. if there is no voltage across the insulation resistance (between high impedance conductor and guard), there cannot be any current flowing through it. the ada4530-1 uses guarding techniques internally, and it has a very high performance guard buffer integrated. the output of this buffer is made available externally to simplify the implementation of guarding at the circuit level. the voltage buffer circuit (see figure 105) has been modified to show the implementation of the guard (see figure 107). in this model, a conductor (v grd ) is added, and it completely separates the high impedance (a) node from the low impedance (b) node at a different voltage. the insulation resistance is modeled as two resistances: all of the insulation between the a conductor and the guard conductor (r shunt1 ), and all of the insulation between the guard conductor and the b conductor (r shunt2 ). the ada4530-1 guard buffer then drives this guard conductor (through pin 2 and pin 7) to the a terminal voltage. if the a node and v grd node are exactly the same voltage, no current flows through the insulation resistance, r shunt1 . in practice, the voltage across r shunt1 cannot be 0 v, the guard buffer offset voltage contributes to the difference in voltage potential between the a node and v grd node. for the ada4530-1 , this offset voltage is trimmed to provide offsets less than 100 v when the input common-mode voltage is 1.5 v from the supply rails. the guard buffer offset voltage and drift are specified in table 1, table 2, and table 3. for example, assume that the voltage sensor produces an output of 1 v. without guarding, the 10 t insulation resistance creates an error current of 100 fa. with the guard, the voltage across the insulation resistance is limited to 100 v. the guard limits the error current to 0.01 fa. in this example, the guard reduces the error by a factor of 10 4 to an insignificant level. ada4530-1 r f r shunt1 r shunt2 r src v src r s 1 2 8 6 v out b a v oltage sensor 7 v grd 13405-313 figure 107. voltage buffer circuit with guard dielectric relaxation dielectric relaxation (also known as dielectric absorption or soakage) is a property of all insulating materials that can limit the performance of electrometer circuits that need to settle to a few femtoamperes. dielectric relaxation is the delay in polarization of the dielectric molecules in response to a changing electric field. this delay is a property of all insulating materials. the magnitude and the time constant of the delay depend on the specific dielectric material. the delays in some materials can be minutes or even hours. dielectric relaxation is a problem for electrometer circuits because small displacement currents flow through the insulator in response to the polarization of the molecules. delays in polarization cause delays in the dissipation of these currents, which can dominate the settling time in these circuits. in the context of capacitors, dielectric relaxation is called dielectric absorption. capacitors are specified with a test that measures the residual open-circuit voltage after a specific charge/discharge cycle. for elec trometer circuits, it is more useful to consider the short-circuit currents produced from step changes in a test voltage. a simple lumped circuit model of an insulator is connected to the test voltage source (see figure 108). the majority of the dielectric polarizes instantly; this is modeled as capacitor c1. a small percentage of the dielectric polarizes slowly with a time constant of 2, modeled as capacitor c2 and resistor r2.
data sheet ada4530-1 rev. a | page 35 of 50 the size of c2 reflects the proportion of slow molecules. the size depends on the material but it is typically 100 to 10,000 times smaller than c1. the size of r2 sets the time constant. 2 = r2 c2 insulato r model r s r2 c2 c1 v src i src 13405-326 figure 108. dielectric relaxation model test circuit v src i src time 1 = r s c1 2 = r2 c2 13405-314 figure 109. step response of dielectric relaxation model the current step response (i src ) of the insulator to a voltage step is shown in figure 108. a large initial current charges capacitor c1 with a fast time constant. this time constant, 1, equals the source resistance r s c1 (see figure 109). long after capacitor c1 is charged, a much smaller current continues to flow, which charges capacitor c2. the time constant of charging is not affected by the external circuitry; it depends only on the material proper- ties of the insulator. the magnitude of the current depends on the magnitude of the voltage change across the insulator. the dielectric relaxation performance was measured for a variety of pcb laminates using the test circuit in figure 108. an electrometer grade source measurement unit (smu), keithley 6430, applies a 100 v test stimulus and measures the resulting current. the large alternating polarity test voltage distinguishes the small dielectric relaxation current from the input offset current of the smu. the first pcb laminate tested is the industry-standard fr-4 glass epoxy. the measurement results are shown in figure 110. the glass epoxy laminate requires 1 hour to dissipate the dielectric relaxation current to less than 10 fa. this result shows that glass epoxy laminates are unsuitable for the highest performance electrometer circuits. 125 ?125 ?100 ?75 ?50 ?25 0 25 50 75 100 20 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 04.0 3.0 3.5 2.5 2.0 1.5 1.0 0.5 applied voltage (v) current (fa) elapsed time (hours) v src i src 13405-315 figure 110. glass epoxy dielectric relaxation performance an alternative pcb laminate to consider is rogers 4350b. rogers 4350b is a ceramic laminate designed for rf/microwave circuits. rogers 4350b is compatible with standard pcb produc- tion techniques and is widely available. the measurement results for the rogers 4350b material are shown in figure 111. this material requires less than 20 sec to dissipate the dielectric relaxation current to less than 1 fa. based on its superior performance, it is recommended to use rogers 4350b laminates with the ada4530-1 in the highest performance applications. all of the critical characterization measurements of the ada4530-1 are taken using rogers 4350b. 125 ?125 ?100 ?75 ?50 ?25 0 25 50 75 100 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0200 120 140 160 180 10080 6040 20 applied voltage (v) current (fa) elapsed time (seconds) v src i src 13405-316 figure 111. rogers 4350b dielectric relaxation performance
ada4530-1 data sheet rev. a | page 36 of 50 humidity effects the insulation resistance of the materials used to construct circuits is sensitive to moisture. at lower temperatures (<70c) the insulation resistance creates more significant leakage current errors than the amplifier itself. this means that the relative humidity of the air is the most important error source at lower temperatures. the dependence on humidity is evident in the input bias current vs. temperature graphs (see figure 34 to figure 36). there is significant deviation in the low temperature measurements due to the difficulty maintaining a consistently low relative humidity at low temperatures. to evaluate the humidity sensitivity of insulation resistance, there are two mechanisms which must be considered: adsorption and absorption. adsorption is a process where thin films of molecules adhere to the surface of a material. water molecules are subject to this process. the magnitude of the effect depends on the insulating material and the relative humidity. thin films of moisture are conductive, and they act as leakage resistances in parallel with the insulation resistance of the material. because this is a surface effect, guard ring techniques are effective at reducing it. absorption is a process where molecules enter the bulk of a material. water molecules can diffuse into a material and affect the bulk conductivity of that material. because the leakage paths are through the bulk of the material, guard rings are not effective at reducing it. it is not possible to completely guard all the leakage paths: bulk or surface. a relevant example of this limitation is the molding compound of the soic package housing the ada4530-1 . surface and bulk paths exist from the input pins to all other pins of the package. the nature of the resulting current depends on the specific leakage path: paths to v+ increase the bias current flowing out of the amplifier, paths to v? increase the bias current flowing into the amplifier, and paths to v out lower the effective feedback resistance in tia circuits. consider the example of a circuit powered from 5 v power supplies with an input common-mode voltage of 0 v. assume that all of the leakage resistance between the input and v+ is effectively 100 t. this resistance creates a current equal to 50 fa flowing from v+. assume that the leakage resistance between the input and v? is effectively 250 t. this resistance creates a current equal to 20 fa flowing to v?. the net current equals ?30 fa flowing out of the input pin. all of these leakage currents can be combined with the amplifier input bias current and treated as an effective input bias current. the effective input bias current sensitivity to relative humidity of the ada4530-1 is characterized for several units. the test amplifiers are configured in tia and unity buffer circuits with 100 g, hermetically sealed resistors (rx-1m1009fe) as the feedback and source resistors, respectively. these glass bodied resistors have a silicone coating (glass has poor humidity adsorption properties). the ada4530-1 amplifiers are mounted on rogers 4350b pcbs (glass epoxy boards have poor humidity absorption properties). figure 112 shows the effective input bias current vs. relative humidity for seven characterization units. figure 112 is plotted with a split log axis to effectively show the magnitude and polarity of the bias current. the magnitude of the leakage currents changes by more than factor of 100 across the relative humidity span from 5% to 80%. the effective bias current is much less than 1 fa for typical conditioned environments (rh < 50%). i b (fa) 100 10 1 0.1 ?0.1 0 20406080 relative humidity (%) ?1 ?10 ?100 ?1000 13405-112 v sy = 10v t a = 25c v cm = v sy /2 7 units figure 112. effective input bias current vs. rela tive humidity the magnitude of the effective input bias current becomes very sensitive to the relative humidity at higher humidity levels (>60%). some of the units show an exponential dependence on humidity (see the blue curve in figure 112). other units show a less predictable dependence; the leakage current magnitude increases rapidly, but the polarity can change. the net leakage current is the sum of the currents sourced from higher voltages (like v+) with the currents sunk by lower voltages (like v?). as the humidity changes, the relative magnitudes of each of these leakage paths can change, which can result in changes in the polarity of the leakage current (see the red and green curves in figure 112). the response time of these leakage currents depends on the physical process that causes them. because adsorption is a surface effect, the film thickness rapidly achieves equilibrium with changes in the relative humidity of the air. because absorption is a bulk diffusion process, it is very slow compared to the adsorption process. these widely different time constants mean that the effective input bias current responds quickly to a step change in relative humidity, but has a very long settling time. the step response of one amplifier to a 50% to 60% relative humidity change is shown in figure 113. the high frequency response of the initial humidity step (and the overshoot recovery) is on the order of seconds to tens of seconds. complete settling takes over a week as the moisture slowly diffuses through the pcb insulation and package molding compound. note that each data point in figure 112 was taken after one week of settling time.
data sheet ada4530-1 rev. a | page 37 of 50 in practical applications, the relative humidity of the air changes rapidly with daily and seasonal variations. the effective input bias current response to these humidity changes has two parts. the response due to the adsorption process follows the rapid changes immediately. the response due to the absorption process low-pass filters the humidity changes. this low-pass response causes the effective input bias current to have long- term memory of the relative humidity fluctuations. in this environment, measurements of the effective input bias current appear to drift with time because the leakage currents depend on the relative humidity for the previous week. this long-term memory due to the absorption process may need to be taken in account in certain circumstances (that is, long-term product storage in an unconditioned high humidity environ- ment prior to use). the rapid adsorption response can change the effective bias current in response to local fluctuations in humidity. these current fluctuations can be much larger than the low frequency current noise of the amplifier and thermal noise of the resistors. the sensitive circuitry can be isolated from these local humidity fluctuations by restricting the airflow around the circuitry with an air baffle. electrostatic shielding added to reduce interfer- ence can also function as an air baffle. remove or reduce the sources of humidity fluctuations whenever possible. avoid breathing on the high impedance circuitry, for example. 6 ?8 ?6 ?4 ?2 0 2 4 70 0 10 20 30 40 50 60 0 175 150 125 100 75 50 25 i b (fa) relative humidity (%) elapsed time (hours) v sy = 10v t a = 25c v cm = v sy /2 13405-402 i b relative humidity figure 113. effective input bias current transient response to humidity step it is important to note that all electrometer circuits are subject to humidity effects. the legacy circuits constructed with to-99 packages using air wiring techniques have insulator leakage paths such as the epoxy between the pins and the teflon? standoffs used to support the air wired components. the input bias currents of legacy amplifiers are high enough to mask the humidity effects. in summary, the ada4530-1 can be designed using the specified performance for normal laboratory (<60%) relative humidity conditions. in applications that must operate in uncontrolled or high humidity environments, some additional derating of the input bias current is prudent. characterize the amount of derating on a per product basis because the net leakage depends on the material types and physical dimensions of the insulators. contamination the effective insulation resistance of an electrometer circuit can be substantially degraded if the insulators are contaminated. solder flux, body oils, dust, and dirt are all possible sources of contamination. some of these contaminants form a parallel leakage path across the surface of the existing insulator effec- tively lowering the insulation resistance. guarding techniques help to suppress these effects. the effects are more severe when the source of contamination contains ionic compounds. in the presence of humidity, these contaminates act as an electrolyte, which can form a weak battery. flux residue and body oils are particularly effective at creating these parasitic batteries. as an example, the pcb insulation between two high imped- ance nodes was purposefully contaminated with a 3 mm drop of rosin mildly activated (rma) type solder flux. this sample was dried and allowed to stabilize in laboratory conditions (25c, 40% rh) for several days. after this time, the voltage vs. current relationship was measured with an electrometer grade smu (see figure 114). this contamination formed a weak battery with an open circuit voltage (v batt ) of 15 mv and an output resistance (r batt ) of 300 g. this sort of contamination is disastrous in electrome- ter circuits because guarding techniques cannot suppress it. a simplified model is made with the contamination battery applied across the a terminal and b terminal of a tia circuit (see figure 115). the a terminal and b terminal are both driven to the same voltage, which creates an error current (i batt ) because the open circuit battery voltage is dropped across the output resistance as follows: i batt = v batt r batt all of this battery current flows through the feedback resistance, where it is summed with the signal and other error currents in the circuit. the error current in this example is 50 fa. the battery characteristics are subject to the environmental conditions; therefore, the error current drifts with time, temperature, and humidity.
ada4530-1 data sheet rev. a | page 38 of 50 400 ?400 ?300 ?200 ?100 0 100 200 300 ?100 100 20 40 60 80 0 ?20?40 ?60 ?80 output current (fa) applied voltage (mv) 13405-319 figure 114. current to voltage response of rma contaminated insulation 13405-312 ada4530-1 r batt v batt 8 1 6 v out b a r f i batt battery model figure 115. tia circuit with contamination battery cleaning and handling the contamination described in the contamination section can usually be removed by an appropriate cleaning process. solvents like isopropyl alcohol (ipa) are effective at removing the residue from solder fluxes and body oils. use high purity cleanroom grade solvents to ensure that there is no additional contamina- tion from the solvent itself. insulators that are severely contaminated benefit from mechani- cal abrasion in addition to the solvent. ultrasonic cleaners are highly effective. scrubbing the area around the high impedance insulators with an acid brush also works. flush the insulators with a final wash of fresh ipa to remove any contaminants suspended in the solvent. the residual moisture must be allowed to completely evaporate before the insulator can be used. this evaporation may take many hours at room temperature; the process can be accelerated by baking the insulators in an oven at elevated temperature. for detailed cleaning and handling procedures, refer to the ada4530-1r-ebz user guide . solder paste selection solder paste selection can drastically impact the performance of the board if not cleaned properly. solder flux residue on a pcb degrades the low i b performance of the amplifier. an experiment was performed to evaluate the cleaning procedure for different solder paste types. table 7 shows the result of the experiment. the recommended cleaning procedure column lists the times required to restore the effective input bias currents to less than 1 fa. the suggested solder paste of choice is the rma type. table 7. recommended cleaning procedures for different solder paste material solder paste type solder paste part number recommended cleaning procedure 1 rma aim rma258-15r 15 min clean time in an ultrasonic cleane r with fresh ipa, followed by 1.5 hours of bake time at 125c water soluble sac305 shenmao 1.5 hours clean time in an ultrasonic cleaner with fresh ipa, followed by 1.5 hours of bake time at 125c no clean sac 305 amtech lf4300 3 hours clean time in an ultrasonic cleane r with fresh ipa, followed by 3 hours of bake time at 125c 1 bake time was not optimized and was set equal to the cleaning time.
data sheet ada4530-1 rev. a | page 39 of 50 current noise considerations the current noise from an amplifier input pin is important when it flows through an impedance and generates a voltage noise. if the current noise and impedance are large enough, the resulting voltage noise can dominate the other noise sources in the circuit such as the voltage noise of the resistors and amplifier. for an electrometer amplifier such as the ada4530-1 , the typical circuit impedances are so large that the current noise of the amplifier can be the most important noise source. to measure current noise, it is necessary to flow the noise current through a test impedance large enough that the resulting noise voltage is larger than the other noise voltages in the circuit. practically, this test impedance is usually a resistor. all resistors have their own thermal noise. the value of thermal noise is usually presented as an output referred voltage noise spectral density (nsd), v nrto . v nrto = (4k tr ) where: k is boltzmanns constant. t is the temperature in kelvin. r is the resistance value. the resistor thermal noise can be interpreted as a current nsd by dividing the thermal noise with the resistance value, r, per ohms law. table 8 shows the thermal noise of a series of resistor values presented as both voltage and current noise. the current noise of a resistor decreases as the resistance increases. this surprising result illustrates that it is necessary to use high valued resistors to measure low levels of current noise. table 8. resistor thermal noise resistor value voltage noise current noise 1 m 128 nv/hz 128 fa/hz 100 m 1.28 v/hz 12.8 fa/hz 10 g 12.8 v/hz 1.28 fa/hz 1 t 128 v/hz 128 aa/hz the measurement setup used to gather the current noise data is shown in figure 116. the ada4530-1 is configured as a tia with a large value feedback resistor, r f . all amplifier current noise from the inverting input flows through resistor r f to produce a voltage noise at v out . r f c f ada4530-1 sr785 dsa v out 13405-305 figure 116. current noise measurement setup the output referred voltage nsd, v nrto , is sampled by the sr785 high performance dynamic signal analyzer (dsa) and is equal to the root-sum-square of the amplifier current noise multiplied by r f , the resistor thermal noise, and amplifier voltage noise. v nrto = (( i n? r f ) 2 + 4k tr f + v n 2 ) where: i n? is the amplifier inverting current noise. 4k tr f is the resistor thermal noise. v n 2 is the amplifier voltage noise. calculate the current noise of the amplifier from v nrto as follows: f nf nrto n r vktr v i 2 2 4 ?? ? ? (1) for equation 1 to be valid, the measured noise must be somewhat larger than the resistor thermal noise plus the amplifier voltage noise. in practice, ensure that the resistor current noise is less than or equal to the amplifier current noise. for example, if the amplifier noise is expected to be 2 fa/hz, use a value of r f that is at least 10 g, according to table 8. the amplifier voltage noise is not a concern at most frequencies because the resistor thermal noise is much larger than the amplifier voltage noise. at very low frequencies, this assumption is not valid due to the 1/f characteristic of the amplifier voltage noise. it is important to consider the bandwidth limitations of the current noise measurement system shown in figure 116. the presence of stray capacitance makes it impossible to maintain the high impedances required for the measurement. all stray capacitance that couple the amplifier output to the inverting input can be lumped into a single capacitor, c f , as shown in figure 116. the current noise must pass through r f to become voltage noise. however, in practice, the current noise passes through the parallel combination of r f and c f to become voltage noise. at frequencies higher than the r f c f pole, most of the noise current flows through the capacitor and current noise calculations at these frequencies are error prone due to the distributed parasitic nature of c f . a good guideline is to set the measurement band- width limit equal to the r f c f pole frequency. the measurement bandwidth limitations for high valued resistors can be surprisingly low. table 9 shows the ?3 db bandwidth of a series of resistor values with a practical minimum stray capacitance value. table 9. bandwidth limitations resistor value capacitor value ?3 db bandwidth 1 m 100 ff 1.59 mhz 100 m 100 ff 15.9 khz 10 g 100 ff 159 hz 1 t 100 ff 1.59 hz
ada4530-1 data sheet rev. a | page 40 of 50 reconsider the example amplifier with 2 fa/hz of current noise. the required r f value of 10 g also limits the measurement bandwidth to 159 hz according to table 9. it is useful to construct a table that combines the resistor noise and measurement bandwidth guidelines. table 10 shows the approximate bandwidth limitations for a variety of input current noise measurements. table 10. measurement current noise density vs. bandwidth current noise density bandwidth 128 aa/hz 1.59 hz 1.28 fa/hz 159 hz 12.8 fa/hz 15.9 khz 128 fa/hz 1.59 mhz table 10 demonstrates the error of the often claimed 0.1 fa/hz at 10 khz presented in the specifications of low input bias current amplifiers. measuring this value requires a 1 t resistor with less than 15.9 af (15.9 10 ?18 f) of stray capacitance, which is impossible. these kinds of claims are simply shot noise calculations based on the specified input bias currents of a few tens of femtoamperes. calculate the shot noise of a semiconductor as follows: shot noise = (2qi b ) where: q is the charge on an electron. i b is the current flowing through a junction. shot noise calculations are appropriate only for some legacy jfet-based electrometer amplifiers, where only a single junction is connected to the amplifier input pins. modern high impedance amplifiers have several semiconductor junctions connected to the amplifier input pins. the most significant of these junctions are the esd diode structures. the input bias currents are equal to the sum of these diode currents. the diode currents are designed to cancel each other, but the shot noise currents are uncorrelated and cannot cancel, which, in turn, makes calculating the shot noise from the input bias current impossible. even when appropriate, these shot noise calculations neglect all capacitive coupling effects so that they are valid only at very low frequencies. the gate to source capacitance of the input transis- tors couples noise currents from sources other than the input junctions for frequencies above a few tens of hertz. this blowback noise effect is present in all amplifiers, and it ensures that the current nsd always increases as frequency increases. the complex relationship between current noise, feedback resistance, and bandwidth means that the proper way to characterize the current noise of an electrometer amplifier is by measuring the output nsd with a variety of feedback resistors that cover the entire span of values used in the end applications. each feedback resistor establishes a boundary for the minimum measurable current noise over a range of frequencies. it is critically important to use high quality resistors during this measurement. many high valued resistors designed for high voltage operation are nonlinear at low voltage levels and are not suitable for electrometer work. inferior resistors may also have their own 1/f noise that corrupts the measurement results. table 11 lists the resistors used for the characterization of the ada4530-1 . table 11. test resistor device numbers resistor value manufacturer device number 100 m vishay rnx050100mdhlb 1 g ohmite rx-1m1007ge 10 g ohmite rx-1m1008je 100 g ohmite rx-1m1009fe 1 t ohmite rx-1m100ake figure 117 shows the output referred voltage nsd (v nrto ) of the transimpedance test circuit for the test resistors listed in table 11. the calculated thermal noise for each resistor is represented with the dashed line. the black dashed line represents the 1/f voltage noise of the amplifier. 100 1 10 100 10 1 0.001 100k 10k 1k 100 10 1 0.1 0.01 total output voltage noise density (v/ hz) input series resistor thermal noise (v/ hz) frequency (hz) v sy = 10v a v = +1 1/f 1t ? 100g ? 10g ? 1g ? 100m ? 13405-306 figure 117. transimpedance nsd referred to output v nrto is dominated by the resistor noise for all of the test resistors up 1 t. this means that the current noise contribu- tion from the ada4530-1 is insignificant relative to the thermal noise of these resistors. it is possible to calculate the current noise of the ada4530-1 with the 1 t resistor. this result is shown in figure 118. it is impossible to calculate the amplifier current noise for all of the other resistors. the most that can be said is that the amplifier current noise is much less than the resistor noise. the current noise densities of each of the test resistors are plotted as dashed lines in figure 118. the current noise of the ada4530-1 is below the resistor noise values.
data sheet ada4530-1 rev. a | page 41 of 50 100 0.01 0.1 1 10 0.001 100k 10k 1k 100 10 1 0.1 0.01 current noise density (fa/ ? 100g ? 10g ? 1g ? 100m ? 13405-307 figure 118. current noise spectral density the current noise of the ada4530-1 originates from the saturation current of the esd diodes. the diode saturation current has an exponential dependence on temperature; therefore, it is expected that the current noise tracks this temperature behavior. the current noise of the ada4530-1 is characterized over temperature using the transimpedance measurement circuit with a 1 t resistor. the measurements are limited to 85c because of the maximum operating temperature of the resistor. figure 119 shows the current noise density at a frequency of 0.1 hz for all of the test temperatures. it can be useful to calculate an equivalent noise resistance from the current noise density data in figure 119. this conversion facilitates comparisons between the current noise generated by the ada4530-1 and the thermal noise of the feedback resistor used in the circuit. 800 0 200 400 600 700 100 300 500 090 80 706050 4030 2010 current noise density (aa/ 13405-308 figure 119. current noise density vs. temperature figure 120 shows the equivalent noise resistance vs. temperature. from figure 120, it is simple to determine that the ada4530-1 contributes less noise than a 1 t resistor for temperatures less than 40c. if the application requires 85c operation, the ada4530-1 contributes as much noise as a 30 g resistor. this example illustrates the considerable impact that temperature plays in determining the noise performance of an application. 10t 10g 100g 1t 090 80 706050 4030 2010 equivalent noise resistance ( ? ) temperature (c) f = 0.1hz 13405-309 figure 120. equivalent noise resistance vs. temperature in summary, the excellent noise performance of the ada4530-1 makes it ideal for electrometer applications. for impedances less than 1 t, the amplifier noise is negligible. also, unlike other amplifiers, the current noise has been fully characterized and is free of excessive blowback noise.
ada4530-1 data sheet rev. a | page 42 of 50 layout guidelines physical implementation of guarding techniques in the guarding section, guarding was introduced as a tech- nique fundamental to high impedance work. the goal of guarding is to completely surround the insulation of high impedance node with another conductor that is driven to the guard voltage. this ideal is impossible to achieve in practice; however, there are several practical structures that provide good performance. guard ring a guard ring is a structure typically used to implement the guarding technique on the surface of the pcb. a simplified layout of the buffer circuit implements the guard ring around the high impedance (a) trace (see figure 121). the output of the voltage sensor is wired directly to the a and b pads in figure 121. the guard ring is a filled copper shape that completely surrounds the high impedance (a) trace from the sensor connection to the noninverting input (pin 1). the guard ring is driven directly from the ada4530-1 guard buffer (pin 2) through a thermal relief shape connection. it is not necessary to connect the other guard buffer output (pin 7). the solder mask was removed from the high impedance trace and the guard trace to ensure that the guard makes electrical contact with any surface leakage paths. for the same reason, avoid printing any silkscreen in this section. vout v? v+ b a guard rf gnd c+ c? rs 13405-320 ada4530-1 figure 121. buffer circuit layout there is not a large amount of exposed insulation between the a trace and the guard ring. it is often counterproductive to increase this spacing to try to increase the insulation resistance because the exposed insulator tends to accumulate surface charges generated from piezoelectric or triboelectric effects. these charges are eventually swept across the insulator toward the high impedance conductor. the magnitude of this error current is dependent on the area of the exposed high impedance insulation. a gap of 15 mil between the a trace and the guard ring is sufficient. another simplified layout demonstrates the implementation of a guard ring in the tia circuit (see figure 122). the guard ring is implemented in the same manner as the buffer circuit. the primary difference is that the left half of the feedback resistor (rf) and feedback capacitor (cf) are connected to the high impedance node. the guard ring shape is extended around these passive components to ensure that the entire high impedance node is surrounded by guard. the guard ring is directly driven from the ada4530-1 guard buffer (pin 7). ada4530-1 vout v? v+ b a guard rf cf gnd c+ c? 13405-321 figure 122. tia circuit layout the guard voltage in the tia circuit is nominally equal to the b voltage, which makes it possible to drive the guard ring directly from the b voltage without using the ada4530-1 guard buffer. when implementing the guard ring this way, do not make any connection to the guard buffer outputs (pin 2 and pin 7). guard plane a guard plane is a structure used to implement the guarding technique through the bulk of the pcb. the structure of the guard plane is shown in a cross section of the pcb (see figure 123). the guard plane is a filled copper shape that is placed directly below the high impedance (a) trace. this plane is connected to the guard ring on the surface layer with vias. if the circuit board is constructed using high performance pcb laminates such as rogers 4350b, a hybrid stackup is required for mechanical strength. the outside layers are ceramic, whereas the core layers are conventional glass epoxy laminate. it is important to place the guard shield on the boundary of the ceramic and glass epoxy materials to protect the high impedance node from the poor dielectric relaxation characteristics of the glass epoxy materials.
data sheet ada4530-1 rev. a | page 43 of 50 13405-322 a guard guard guard fr-4 rogers 4350b solder mask solder mask figure 123. layout cross section with guard plane via fence a via fence is an additional structure that guards the lateral leakage paths in the laminate between the guard ring and the guard plane (see figure 123). the fence is implemented by surrounding the entire guard ring with vias that connect the guard ring to the guard plane (see figure 121 and figure 122). cables and connectors guarding techniques are required for all of high impedance wiring; not just on the pcb. frequently, the high impedance sensor is not directly mounted on the pcb with the electrome- ter amplifier and external cables are used to make the connection. the typical way to guard a cable connecting to a current output sensor is by using a coaxial cable. a coaxial cable consists of an inner conductor surrounded with insulation, which is, in turn, surrounded by a braided conductor. use the inner conductor for the high impedance (a) terminal and the outer braided shield conductor for the low impedance (b) terminal. conven- iently, this arrangement effectively guards the coaxial insulation resistance because the a terminal and b terminal are nominally at the same voltage (when attached to a tia interface circuit). voltage output sensors are more problematic because the a terminal and b terminal are not at the same voltage. the typical way to guard the voltage output sensor cable is to use triaxial cable. triaxial cable is constructed with an inner conductor with two separate braided conductors. each of these braided conductors is separated from each other with insulation. use the inner conductor for the high impedance (a) terminal and the inner braided conductor for the guard (v grd ) connection, and use the outer braided conductor for the low impedance (b) terminal. all the insulation around the inner conductor is completely surrounded by the guard conductor, which keeps the voltage drop across this insulation equal to zero. electrostatic interferance very high impedance electrometer circuits are susceptible to interference through capacitive coupling. the amount of capaci- tance required to couple low frequency signals is surprisingly small. for example, line frequency (60 hz) interference is coupled (with a ?3 db loss) to a 1 t impedance with only 3 ff of coupling capacitance. traditional electrical interferers are not the only sources of concern. calculate the displacement current, i, in a capacitor as follows: t c v t v ci ? ? ? ? ? ? (2) the second term in this equation is frequently ignored in most circuits, but it can generate some unusual problems in electrome- ter circuits. the problem is that the movement of any charged object changes the coupling capacitance between the object and the electrometer, and this change in capacitance injects small currents into the circuit. the ada4530-1 is so sensitive that it easily detects the movement of a hand or the movement of a piece of paper. these types of effects are not periodic or predictable, and they can appear as erratic dc shifts on the time scales of interest. both of these types of interference can be reduced by the addition of a shield. a shield is a piece of conductive material placed between the high impedance input and the interference source. this shield must be electrically connected to a low impedance source (such as signal ground). if the shield physi- cally interrupts all of the capacitive coupling paths, all of the displacement current from the interference source is shunted to the low impedance source. notice that the construction of a shield is almost the same as the construction of a guard. because of this similarity, many guard structures also provide shielding as well. the primary difference is that the dc voltage of the shield is not important, whereas the guard must have a voltage equal to that of the high impedance input. shields that are driven by the guard buffer have the added benefit of bootstrapping the capacitance between the high impedance input and the shield. the disadvantage of this approach is that the guard buffer output impedance is 1 k, which makes the shield less effective than a signal ground or a chassis ground connection. the most effective systems typically use the box within a box construction: the outer shield is driven with ground and the inner shield is driven with guard. there is another capacitive interference effect that typically cannot be shielded. this displacement current is generated from a change in capacitance with respect to time (the second term of equation 2). this change is due to the mechanical movement of the circuit components. this movement, which can be caused by mechanical impact or vibration, generates electrical interference. this interference typically appears at unexpected frequencies that are equal to the mechanical resonances of the components. this effect must be considered when using traditional air wiring techniques for large feedback resistors or relays. it is important to ensure solid mechanical connections to teflon standoffs for this type of construction.
ada4530-1 data sheet rev. a | page 44 of 50 photodiode interface the low input bias current and low input offset voltage makes the ada4530-1 an excellent choice for signal conditioning photodiodes at extremely low illumination levels. figure 124 shows the ada4530-1 configured in a transimpedance ampli- fier interfacing with a photodiode operating in photovoltaic mode (photodiode is zero biased). a photodiode produces an output current proportional to the illumination level. the amplifier converts the signal current, i pd , into an output voltage with the following equation: v out = i pd r f r f c f v out photodiode i pd 13405-323 figure 124. transimpedance amplifier with photodiode figure 125 replaces the photodiode with an equivalent circuit model. i pd is the photo current generated by incident light and is proportional to the light level. the shunt capacitance (c shunt ) models the depletion capacitance of the diode. this capacitance depends on the area of the photodiode and the voltage bias. the shunt resistance (r shunt ) represents the voltage vs. current slope of the exponential diode curve near zero bias voltage. 13405-324 r f c f v out photodiode r shunt c shunt i pd figure 125. transimpedance amplifier with photodiode model dc error analysis all of the errors described in the high impedance measurements section related to tia circuits are applicable to photodiode interfaces. the inverting input bias current, i b? , sums directly with the photodiode current for a referred to input (rti) error equal to i b? . this current flows through the feedback resistor, creating a referred to output (rto) error equal to v ib_rto = i b? r f the amplifier offset voltage, v os , is a major error source in photodiode interface circuits because of the relatively low shunt resistance of large area photodiodes. typical values are in the range of 1 g to100 g at 25c. more importantly, the shunt resistance decreases by half for every 10c increase in tempera- ture. an error current is created because the amplifier offset voltage is applied across this shunt resistance, resulting in an rti error equal to i vos_rti = v os /r shunt it is equivalent to think that the shunt resistance increases the dc noise gain which multiplies the offset voltage to the output. the rto error due to v os is equal to: v os_rto = v os noise gain v os_rto = v os (1 + r f /r shunt ) the amplifier input resistance and insulation resistance appear in parallel with the photodiode shunt resistance. these addi- tional resistances reduce the effective shunt resistance, but they are much larger than the photodiode shunt resistance and can usually be ignored. ac error analysis photodiode tia circuits typically require external compensation to give satisfactory dynamic performance. the large feedback resistor (r f ) interacts with the large photodiode capacitance (c shunt ) to create a low frequency pole in the feedback network. photodiode shunt capacitance, amplifier input capacitance, and trace capacitance are lumped into a single element, c shunt . the phase shift due to this pole must be recovered prior to the crossover frequency for the feedback loop to be stable. the usual method to recover this phase shift is to create a zero in the feedback factor with the addition of the feedback capacitor (c f ). the classic way of analyzing this circuit is by examining the noise gain vs. frequency (see figure 126). at low frequencies, the noise gain is determined by the ratio of the feedback to the shunt resistance. shunt 1 r rf ng ?? 1 the troublesome low frequency pole (which is a zero in the noise gain) occurs at frequency f 1 . from this frequency onward, the noise gain increases. if there is no feedback capacitor in the circuit, the noise gain follows the dotted line until it intersects with the amplifier open-loop gain curve. if these curves intersect at the 20 db/decade slopes shown in figure 126, the circuit is unstable. the addition of c f adds a zero to the feedback factor (which is a pole in the noise gain) at frequency f 2 . beyond frequency f 2 , the noise gain is determined by the ratio of the shunt capacitance to the feedback capacitance. f shunt 2 c c ng ?? 1
data sheet ada4530-1 rev. a | page 45 of 50 gain (db) frequency (hz) closed-loop bandwidth signal bandwidth if c f =0ff ng 2 ng 1 noise gain open-loop g a in f 1 f ugc f 2 f 3 13405-325 figure 126. transimpedance noise gain vs. frequency for completeness, the noise gain equations are as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? 1 2 1 2 1)( 2 1 s f f f f f r r fng ? ? ?? shunt f shunt f shunt f 1 cc rr rr f ? ? ? 1 ff 2 cr f 1 ? for simplicity, bandwidth limitations are ignored in the noise gain equations. the noise gain starts to roll-off when it intersects with the open-loop gain of the amplifier. this pole frequency (f 3 ) is determined by the unity gain crossover frequency (f ugc ) of the amplifier and the high frequency noise gain, ng 2 , as follows: ? ? ? ? ? ? ? ? ? ? f shunt ugc c c f f 1 3 (3) the addition of c f has an impact on the signal frequency response. at low frequencies, the transimpedance gain is equal to r f . as the frequency increases, the impedance of c f drops below r f and starts to reduce this transimpedance gain. this signal gain equation is as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 1 )( 2 f f f rfgainsignal ? noise analysis photodiode tia circuits have four noise sources that must be considered: ? the thermal noise of the feedback resistor (r f ) ? the saturation current noise of the photodiode ? the current noise of the amplifier ? the voltage noise of the amplifier the noise contributions of these sources are typically referred to output for analysis. the thermal noise of r f appears directly at the output. this noise is filtered by the feedback capacitance so that its ?3 db bandwidth is the same as the signal bandwidth (f 2 ). the photocurrent of a photodiode, i pd , produces shot noise equal to i npd = (2 qi pd ) it is a mistake to assume that the noise goes to zero as the diode current goes to zero. zero net current out of the diode simply means that the saturation current flowing in one direction is at thermal equilibrium with the saturation current flowing in the opposite direction. these currents are uncorrelated and add in a root sum square fashion. this net current noise is equivalent to the thermal noise of a physical resistor with a value of r shunt . this convenient fact allows the photodiode to be accurately modeled with a simple resistor, r shunt . the thermal noise of r shunt is amplified by the ratio of the feedback resistance to the shunt resistance. this noise is also filtered to the signal bandwidth. the current noise of the amplifier flows through the feedback resistor to become a noise voltage at the output. it is subject to the same bandwidth limitations as the previous noise contributors. the voltage noise of the amplifier is multiplied by the noise gain of the circuit to the output. this noise source is significant for two reasons. first, the high frequency noise gain can be high due to the large ratio between the shunt capacitance and the feedback capacitance. second, the voltage noise bandwidth is much higher than the other contributors. the noise bandwidth is limited only by bandwidth of the amplifier.
ada4530-1 data sheet rev. a | page 46 of 50 each of these noise contributors is graphed vs. frequency in figure 127. a summary of the noise sources and their rto contributions is shown in table 12. the total rto noise adds the contributions of each noise source in root sum square. 13405-404 frequency nsd (v/ figure 127. photodiode tia rto noise spectral density table 12. photodiode interface noise sources noise source rto noise noise bandwidth r f (4ktr f ) /2 f 2 photodiode (r f /r shunt )(4ktr shunt ) /2 f 2 i n? amplifier r f i n? /2 f 2 v n amplifier v n noise gain /2 f 3 design recommendations the design goal for a large area photodiode tia circuit is usually to maximize snr and minimize dc errors. increasing the feedback resistor size accomplishes both goals. the signal gain increases directly with r f , whereas the noise increases in a square root fashion. high gains also make the output signal large relative to output voltage errors (such as v os ). the upper limit for r f is typically determined by one of the following: x amplifier output swing. the maximum photocurrent multiplied by r f must be less than amplifier swing limitations. x signal bandwidth (or settling time). signal bandwidth is dependent on r f c f . achieving high signal bandwidths with large feedback resistors can require vanishingly small feedback capacitors to implement. the ultimate limitation is due to the parasitic feedback capacitance from the fringing electric fields in the circuit. parasitic capacitances in the 50 ff to 100 ff range are possible. to put this in perspective, a 100 ff parasitic capacitance limits the signal bandwidth of a 100 g tia to 16 hz. x the thermal noise of the photodiode (r shunt ). when r f is significantly larger than r shunt , the total noise is domi- nated by the photodiode and the snr stops improving. x the current noise of the amplifier. when the current noise of the amplifier is larger than the noise of r f , the snr stops improving. the photodiode noise is higher than the amplifier current noise in nearly all practical photodiodes. x the low frequency noise gain due to r shunt . when r f is larger than r shunt , the noise gain multiplies v os and tcv os errors and the signal to error ratio stops improving. the signal bandwidth increases as the feedback capacitance (c f ) decreases. the lower limit for c f is typically limited by one of the following: x parasitic feedback capacitances limit the minimum value of c f to 50 ff to 100 ff. x available component values. physical components can be found in surface mount packages for values from 0.1 pf to 1 pf in 100 ff increments. x feedback loop stability. c f must be large enough to recover enough phase shift prior to the loop crossover for stable operation. this capacitance value can be a significant consideration for smaller values of r f . large values (>1 g) tend to be self compensating through the parasitic feedback capacitance. x high frequency noise gain. the high frequency noise gain is set by the ratio of c shunt to c f . for very large noise gains, it is possible for the amplifier voltage noise to be greater than the feedback resistor noise. design example in this section, an example tia circuit is designed using a photometry grade photodiode (hamamatsu s1226-18bq). this medium area (1.2 mm 2 ) silicon photodiode is responsive in the ultraviolet (uv) through visible frequency range. the mini- mum shunt resistance (r shunt ) is specified at 5 g at 25c. the shunt capacitance (c shunt ) is specified at 35 pf. the quartz window limits the maximum operating temperature to 60c. based on the specified minimum shunt resistance and the recommendations in the design recommendations section, a value of 10 g is chosen for r f . this example circuit is powered from 5 v with the input common-mode voltage set at 0 v, which allows a maximum photocurrent of approximately 500 pa. an error budget is constructed based on the dc error analysis section (see table 13). the amplifier offset voltage applies the maximum temperature drift limit to the maximum room temperature offset limit. the photo diode shunt resistance limit is reduced by half for every 10c. table 13. photodiode interface dc error budget error source 25c 45c 60c v os 40 v 40 v + 10 v 40 v + 18 v r shunt 5 g 1.25 g 442 m noise gain 3 9 23 v os error rto 120 v 450 v 1.3 mv i b 20 fa 20 fa 20 fa i b error rto 200 v 200 v 200 v total error rto 320 v 650 v 1.5 mv total error rti 32 fa 65 fa 150 fa
data sheet ada4530-1 rev. a | page 47 of 50 the total rti error over the entire temperature range is less than 150 fa, which is equal to 300 ppm of the 500 pa full-scale range. note that the extraordinarily low input bias current of the ada4530-1 is not a significant contributor to the total error over temperature. the interaction of the offset voltage with the shunt resistance of the photodiode is the most significant error source. this circuit was constructed as described with a 10 g feed- back resistor (ohmite rx-1m1008je). the dc error performance was measured over the 25c to 60c temperature range (see figure 128). the error increases rapidly with temperature as the shunt resistance changes the noise gain exponentially. the total rti error ranges from +2 fa to ?10 fa, considerably lower than the worst case error budget, as expected. 20 ?120 ?100 ?80 ?60 ?40 ?20 0 2 ?12 ?10 ?8 ?6 ?4 ?2 0 070 60 50 40 30 20 10 rto error (v) rti error (fa) temperature (c) v sy = 10v v cm = v sy /2 13405-401 figure 128. dc error vs. temperature the ac performance of the circuit was also measured. the circuit was initially constructed without a physical feedback capacitor as a baseline. the transimpedance gain vs. frequency is shown in figure 129. the 30% frequency peaking seen in the frequency response (red curve) indicates that the feedback loop is marginally compensated with parasitic capacitance. a physical capacitor was added to improve the loop compensa- tion. this capacitor is a 300 ff c0g ceramic in a size 0805, surface-mount package (avx uqcfva0r3bat2a\500). c0g ceramic capacitors are good candidates for electrometer circuits because they have adequate insulation resistance and dielectric absorption performance. these low valued capacitors are designed for rf use and are readily available. the 300 ff capacitor elimi- nates the frequency peaking completely (blue curve) but it reduces the ?3 db bandwidth from 390 hz to 50 hz. 0.1 1 10 0.1 1 10 100 1k 10k 100k transimpedance gain (g ? ) frequency (hz) v sy = 10v v cm = v sy /2 t a = 25c 13405-407 c f = 0ff c f = 300ff figure 129. transimpedance gain vs. frequency the stability improvement can be seen in the time domain as well. the circuits step response to a 10 pa photocurrent is shown in figure 130. the uncompensated circuit (red curve) shows considerable (20%) overshoot. the compensated circuit (blue curve) is overdamped. 40 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 4 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 04 0 35 30 25 20 1510 5 output voltage (mv) input referred current (pa) time (ms) v sy = 10v t a = 25c i pd = 10pa 13405-400 c f = 0ff c f = 300ff figure 130. 10 pa step response a noise budget is constructed based on the noise analysis section. the rto noise budget is separated into noise sources integrated with a low bandwidth (see table 14) and those integrated with a high bandwidth (see table 15). the low frequency noise contributors include the feedback resistance, the shunt resistance and the amplifier current noise. each of these sources has a ?3 db bandwidth equal to the signal bandwidth (50 hz); this is equi valent to a noise bandwidth of 79 hz. the most significant noise source is the photodiode shunt resistance by a large margin. the second most significant source is the feedback resistor. the amplifier current noise is so low that it can be ignored.
ada4530-1 data sheet rev. a | page 48 of 50 table 14. low frequency noise budget error source 25c 45c 60c v nrf 12.8 v/hz 13.2 v/hz 13.5 v/hz r shunt 5 g 1.25 g 442 m v nrshunt 9 v/hz 4.7 v/hz 2.8 v/hz r f /r shunt 2 8 22 v nrshunt_rto 18 v/hz 37 v/hz 61 v/hz i n? 0.07 fa/hz 0.15 fa/hz 0.24 fa/hz i n?_rto 700 nv/hz 1.5 v/hz 2.4 v/hz low frequency nsd total 22 v/hz 39 v/hz 62 v/hz low frequency rms total 194 v rms 345 v rms 549 v rms the sole high frequency noise contributor is the amplifier voltage noise, which is multiplied by the high frequency noise gain and band limited only by the amplifier gain. the ?3 db bandwidth of the amplifier is 17 khz (refer to equation 3, where f 3 = f ugc ng 2 = 2 mhz 118). the equivalent noise bandwidth is 27 khz. the high bandwidth is the reason the high frequency noise is significant even though the noise spectral density is much lower than the low frequency noise. table 15. high frequency noise budget error source 25c 45c 60c v n 14 nv/hz 14.5 nv/hz 14.8 nv/hz high frequency noise gain 118 118 118 v n_rto 1.6 v/hz 1.7 v/hz 1.7 v/hz high frequency rms total 271 v rms 281 v rms 286 v rms at low temperatures, the amplifier voltage noise is more signifi- cant than any other noise source. this is important because the majority of this noise occurs outside the useful bandwidth of the circuit. for this reason, it is prudent to add a low-pass filter to the output of a photodiode tia circuit. this filter can be active or passive depending on the needs of the system. a simple rc filter with a ?3 db cutoff of 500 hz has an insignificant impact on the frequency response of the signal path, but it lowers the integrated noise from 271 v rms to 45 v rms (a 6 reduction). the nsd was measured for this circuit with (blue curve) and without (red curve) the 300 ff c f capacitor (see figure 131). at low frequencies, the nsd is approximately equal to the noise from the feedback resistor alone (12.8 v/hz). the value of the low frequency nsd shows that the shunt resistance is much larger than the specified minimum (which is expected). as frequency increases, the resistor noise rolls off at the signal bandwidth (50 hz). the nsd then plateaus at the amplifier voltage noise level until the bandwidth limitations of the amplifier roll off the nsd toward zero. 11 0 10 100 100 1000 0.1 100k 10k 1k 100 10 1 voltage noise spectral density (v/ hz) integrated votlage noise (v rms) frequency (hz) v sy = 10v v cm = v sy /2 t a = 25c 13405-405 nsd, c f = 0ff nsd, c f = 300ff rms, c f = 0ff rms, c f = 300ff figure 131. rto noise sp ectral density (25c) the dashed curves show the integration of the nsd across the frequency spectrum. these are useful to calculate the rms noise over a variety of bandwidths. for example, the rms noise over the entire 100 khz measurement bandwidth is 400 v rms, which is approximately the same as the calculated total noise of 333 v rms. if a postfilter is added with a noise bandwidth of 1 khz, figure 131 shows that the integrated noise is 200 v rms (a 2 improvement). the uncompensated circuit (red curves) shows considerably worse noise performance. the frequency peaking due to the marginal loop stability multiplies the noise as well as the signal. in addition, the high frequency noise gain is larger, which adds much more noise outside the signal bandwidth. both of these effects together generate 1.2 mv rms of total noise. even if the transient and frequency response of an undercompensated tia are acceptable, the large noise penalty may not be. lastly, the nsd was measured for this circuit at 60c (see figure 132). as expected, the low frequency noise increased as a result of the photodiode shunt resistance. the average low frequency nsd is 22 v/hz. removing the contribution of r f gives an rto contribution of 17 v/hz, which is equivalent to an rti current noise of 1.7 fa/hz. r shunt must be approxi- mately 6.5 g at 60c to generate this noise. 11 0 10 100 100 1000 0.1 100k 10k 1k 100 10 1 voltage noise spectral density (v/ hz) integrated votlage noise (v rms) frequency (hz) v sy = 10v v cm = v sy /2 t a = 60c 13405-406 nsd, c f = 300ff rms, c f = 300ff figure 132. rto noise sp ectral density (60c)
data sheet ada4530-1 rev. a | page 49 of 50 power supply recommendations analog devices offers a wide range of power management products to meet the requirements of most high performance signal chains. examples of a single- and dual-supply solution is shown in figure 133. the adp2370 and adp5075 , cascaded with the adp7118 or adm7170 , and the adp7182 generate clean positive and negative rails. these rails power the ada4530-1 , electrometer amplifier and/or the precision converter in a typical signal chain. +5v 3.3v input adp5070 boost and inverting regulator adp7118 ldo adp7182 ldo adp2370 buck regulator +7.5 v or +5v +8.5v or +6v adp7118 ldo adp5075 inverting regulator ?8.5v or ?6v +6v ?6v ?5v adp7182 ldo 15v/12v/6 v input adm7170/ adp7118 ldo +12v/+10v/+5v 12v input ?7.5v or ?5v 13405-533 figure 133. recommended power solutions table 16. recommended power management devices product description adp5075 800 ma, dc-to-dc inverting regulator adp2370 high voltage, 1.2 mhz/600 khz, 800 ma, low quiescent current buck regulator adp5070 1 a/0.6 a, dc-to-dc switching regulator with independent positive and negative outputs adm7170 6.5 v, 500 ma, ultralow noise, high psrr, cmos ldo adp7118 20 v, 200 ma, low noise, high psrr, cmos ldo adp7182 ?28 v, ?200 ma, low noise, linear regulator power supply considerations the psrr of the ada4530-1 is excellent at dc (approximately 150 db); however, it decreases as frequency increases. to achieve the best performance of the ada4530-1 , a low-noise supply is necessary. if switching supplies are used for input rails, a low dropout regulator (ldo) is essential to attenuate the switching spurs to a level that does not affect the ada4530-1 output. switching power supply noise typically spans a frequency range from 300 khz and up. the switching spurs can effectively be attenuated using the ldo. additional filtering around the ldo may be necessary, especially when using a switching regulator to generate an intermediate rail. switching regulators also generate high frequency noise content (>100 mhz), even when running in the 100 khz range, because of the high dv/dt of the switch node. in this case, ferrite beads can be used, as described in the an-1120 application note and the an-1368 application note . for a single-supply application, the ada4530-1 typically needs a 5 v, 10 v, or 12 v supply, although a 4.5 v to 16 v supply can also be used. an ldo like the adm7170 or adp7118 is ideal to generate the low noise rail. for a dual-supply application, the ada4530-1 typically needs a 5 v supply, although in some applications, a 2.5 v to 8 v supply can be used. ldos like the adp7118 or adm7170 are the optimum choices for the positive supply, and the adp7182 for the negative supply. in addition, if a negative supply is not already available, the adp5075 or the adp5070 can generate the negative supply from a positive supply, as shown in figure 133. figure 134 shows the combined psrr of using the adp7118 to provide +5 v on +v sy of the ada4530-1 , and the adp7182 to provide C5 v onCv sy , from a 9 v battery main supply. figure 135 shows the maximum allowable ripple at the input so that the combined psrr of the ldo and the amplifier can still attenuate the noise level down to the noise floor. for example, if the main supply to the adp7118 and ada4530-1 has a switching noise of 20 mv p-p at 300 khz, figure 135 shows that it is below the maximum value of 90 mv p-p. therefore, the combined psrr of the system can still attenuate and bring the noise level down to the noise floor, in effect, the 300 khz noise at the input is not seen at the output of the amplifier. 0 ?120 ?100 ?80 ?60 ?40 ?20 10k 10m 1m 100k psrr (db) frequency (hz) +psrr ?psrr 13405-534 figure 134. positive and negative psrr for the adp7118 and adp7182 powering ada4530-1 , v sy = 5 v, +in = 0 v 100 1000 0.01 0.1 1 10 10 1 0.1 0.01 adp7118 adp7182 frequency (hz) (mv p-p) 13405-535 figure 135. maximum allowable ripple at the input of the ldos to bring spurs to noise floor level (?120 db)
ada4530-1 data sheet rev. a | page 50 of 50 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 136. 8-lead small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ada4530-1arz ?40c to +125c 8-lead small outline package [soic_n] r-8 ADA4530-1ARZ-R7 ?40c to +125c 8-lead small outline package [soic_n] r-8 ada4530-1arz-rl ?40c to +125c 8-lead small outline package [soic_n] r-8 ada4530-1r-ebz-buf evaluation board buffer configuration for 8-lead soic ada4530-1r-ebz-tia evaluation board trans impedance configuration for 8-lead soic 1 z = rohs compliant part. ?2015C2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13405-0-3/16(a)

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